Jianyi Meng

Publication Activity (10 Years)

Years Active: 2015-2023
Publications (10 Years): 32

Top Topics

Wireless Sensor

Error Correction

Lossless Compression

Top Venues

IEICE Electron. Express

IEICE Trans. Inf. Syst.

Publications

Yifan Zhao, Honglin Kuang, Yi Sun, Zhen Yang, Chen Chen, Jianyi Meng, Jun Han
Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography. ASAP (2023)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. CoRR (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. ICPADS (2022)
Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi
Xuantie-910: Innovating Cloud and Edge Computing by RISC-V. Hot Chips Symposium (2020)
Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product. ISCA (2020)
Yin Xu, Zhijian Chen, Feiteng Li, Jianyi Meng
A Granular Resampling Method and Adaptive Speculative Mechanism-Based Energy-Efficient Architecture for Multiclass Heartbeat Classification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (11) (2019)
Huibin Wang, Chunqiang Li, Jianyi Meng, Xiaoyan Xiang
SCSE: Boosting Symbolic Execution via State Concretization. IEICE Trans. Inf. Syst. (8) (2019)
Zhijian Chen, Menghan Jia, Jiahui Luo, Tao-Tao Zhu, Xiaoyan Xiang, Jianyi Meng
A low power QRS detection processor with adaptive scaling of processing resolution. IEICE Electron. Express 15 (1) (2018)
Zhijian Chen, Huanzhang Xu, Jiahui Luo, Tao-Tao Zhu, Jianyi Meng
Low-power perceptron model based ECG processor for premature ventricular contraction detection. Microprocess. Microsystems 59 (2018)
Yande Xiang, Jiahui Luo, Tao-Tao Zhu, Sheng Wang, Xiaoyan Xiang, Jianyi Meng
ECG-Based Heartbeat Classification Using Two-Level Convolutional Neural Network and RR Interval Difference. IEICE Trans. Inf. Syst. (4) (2018)
Jiahui Luo, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng
A Highly Adaptive Lossless ECG Compression ASIC for Wireless Sensors Based on Hybrid Gomlomb Coding. IEICE Trans. Inf. Syst. (3) (2018)
Yin Xu, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng
An energy-efficient parallel VLSI architecture for SVM classification. IEICE Electron. Express 15 (7) (2018)
Zhitao Lin, De Ma, Jianyi Meng, Linna Chen
Relative ordering learning in spiking neural network for pattern recognition. Neurocomputing 275 (2018)
Yan He, Jianyi Meng, Zhijian Chen, Xiaoyan Xiang, Chen Chen
An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs. IEICE Electron. Express 15 (3) (2018)
Yande Xiang, Jianyi Meng
A Cross-layer based mapping for spiking neural network onto network on chip. Int. J. Parallel Emergent Distributed Syst. 33 (5) (2018)
Zhijian Chen, Jiahui Luo, Kaiwen Lin, Jiaquan Wu, Tao-Tao Zhu, Xiaoyan Xiang, Jianyi Meng
An Energy-Efficient ECG Processor With Weak-Strong Hybrid Classifier for Arrhythmia Detection. IEEE Trans. Circuits Syst. II Express Briefs (7) (2018)
Sheng Wang, Chen Chen, Xiaoyan Xiang, Jianyi Meng
A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs. IEICE Electron. Express 14 (11) (2017)
Yin Xu, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng
A granular resampling method based energy-efficient architecture for heartbeat classification in ECG. IEICE Electron. Express 14 (22) (2017)
Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng
A new error masking flip-flop with one cycle correction penalty. ASICON (2017)
Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng
An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Xiaopei Chen, Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng
A light-weight energy-efficient resilient circuit for variation tolerance. ASICON (2017)
Jiahui Luo, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng, Haibin Shen
A dual-mode ECG processor with difference-insensitive QRS detection and lossless compression. IEICE Electron. Express 14 (12) (2017)
Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng
SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor. IEICE Electron. Express 14 (8) (2017)
Jiahui Luo, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng
A lifting wavelet based lossless and lossy ECG compression processor for wireless sensors. IEICE Electron. Express 14 (20) (2017)
Jing Qiu, Xiaoyan Xiang, Zhijian Chen, Jianyi Meng, Yong Ding
Ultralow power processor employing block instruction for ECG applications. IEICE Electron. Express 13 (2) (2016)
Chaojun Zhao, Chen Chen, Zhijian Chen, Jianyi Meng
Value locality based storage compression memory architecture for ECG sensor node. Sci. China Inf. Sci. 59 (4) (2016)
Zhenqiang Yong, Xiaoyan Xiang, Jianyi Meng, Chen Chen
TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor. IEICE Electron. Express 13 (20) (2016)
Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng, Yong Ding, Xiaolang Yan
EDSU: Error detection and sampling unified flip-flop with ultra-low overhead. IEICE Electron. Express 13 (16) (2016)
Li Zhanhui, Yong Ding, Xiaolang Yan, Jianyi Meng, Xiaoyan Xiang
Light-weight one-cycle timing error correction based on hardware software co-design. IEICE Electron. Express 13 (11) (2016)
Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng
A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction. ASICON (2015)
Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng
A timing failure tolerance design with in-field simultaneous error detection and correction. ASICON (2015)
Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng
An energy-efficient microprocessor using multilevel error correction for timing error tolerance. ASICON (2015)