Chen Chen

Publication Activity (10 Years)

Years Active: 2015-2022
Publications (10 Years): 17

Top Topics

Error Correction

Top Venues

IEICE Electron. Express

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Wenhan Cao, Jingliang Duan, Shengbo Eben Li, Chen Chen, Chang Liu, Yu Wang
Primal-dual Estimator Learning: an Offline Constrained Moving Horizon Estimation Method with Feasibility and Near-optimality Guarantees. CoRR (2022)
Zeyu Gao, Yao Mu, Ruoyan Shen, Chen Chen, Yangang Ren, Jianyu Chen, Shengbo Eben Li, Ping Luo, Yanfeng Lu
Enhance Sample Efficiency and Robustness of End-to-end Urban Autonomous Driving via Semantic Masked World Model. CoRR (2022)
Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi
Xuantie-910: Innovating Cloud and Edge Computing by RISC-V. Hot Chips Symposium (2020)
Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product. ISCA (2020)
Yan He, Jianyi Meng, Zhijian Chen, Xiaoyan Xiang, Chen Chen
An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs. IEICE Electron. Express 15 (3) (2018)
Sheng Wang, Chen Chen, Xiaoyan Xiang, Jianyi Meng
A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs. IEICE Electron. Express 14 (11) (2017)
Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng
A new error masking flip-flop with one cycle correction penalty. ASICON (2017)
Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng
An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Xiaopei Chen, Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng
A light-weight energy-efficient resilient circuit for variation tolerance. ASICON (2017)
Sheng Wang, Chen Chen, Xiaoyan Xiang, Jian-Yi Meng
A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 25 (7) (2017)
Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng
SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor. IEICE Electron. Express 14 (8) (2017)
Chaojun Zhao, Chen Chen, Zhijian Chen, Jianyi Meng
Value locality based storage compression memory architecture for ECG sensor node. Sci. China Inf. Sci. 59 (4) (2016)
Zhenqiang Yong, Xiaoyan Xiang, Jianyi Meng, Chen Chen
TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor. IEICE Electron. Express 13 (20) (2016)
Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng, Yong Ding, Xiaolang Yan
EDSU: Error detection and sampling unified flip-flop with ultra-low overhead. IEICE Electron. Express 13 (16) (2016)
Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng
A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction. ASICON (2015)
Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng
A timing failure tolerance design with in-field simultaneous error detection and correction. ASICON (2015)
Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng
An energy-efficient microprocessor using multilevel error correction for timing error tolerance. ASICON (2015)