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Tao-Tao Zhu
ORCID
Publication Activity (10 Years)
Years Active: 2015-2020
Publications (10 Years): 8
Top Topics
Discriminative Classifiers
Collaborative Design
Low Power
Error Resilient
Top Venues
IEICE Electron. Express
IEEE Trans. Very Large Scale Integr. Syst.
IEICE Trans. Inf. Syst.
ASICON
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Publications
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Yan He
,
Zhijian Chen
,
Xiaoyan Xiang
,
Tao-Tao Zhu
A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs.
IEEE Access
8 (2020)
Zhijian Chen
,
Menghan Jia
,
Jiahui Luo
,
Tao-Tao Zhu
,
Xiaoyan Xiang
,
Jianyi Meng
A low power QRS detection processor with adaptive scaling of processing resolution.
IEICE Electron. Express
15 (1) (2018)
Zhijian Chen
,
Huanzhang Xu
,
Jiahui Luo
,
Tao-Tao Zhu
,
Jianyi Meng
Low-power perceptron model based ECG processor for premature ventricular contraction detection.
Microprocess. Microsystems
59 (2018)
Yande Xiang
,
Jiahui Luo
,
Tao-Tao Zhu
,
Sheng Wang
,
Xiaoyan Xiang
,
Jianyi Meng
ECG-Based Heartbeat Classification Using Two-Level Convolutional Neural Network and RR Interval Difference.
IEICE Trans. Inf. Syst.
(4) (2018)
Zhijian Chen
,
Jiahui Luo
,
Kaiwen Lin
,
Jiaquan Wu
,
Tao-Tao Zhu
,
Xiaoyan Xiang
,
Jianyi Meng
An Energy-Efficient ECG Processor With Weak-Strong Hybrid Classifier for Arrhythmia Detection.
IEEE Trans. Circuits Syst. II Express Briefs
(7) (2018)
Tao-Tao Zhu
,
Jian-Yi Meng
,
Xiaoyan Xiang
,
Xiaolang Yan
Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor.
IEEE Trans. Very Large Scale Integr. Syst.
25 (5) (2017)
Zhan-Hui Li
,
Tao-Tao Zhu
,
Zhi-Jian Chen
,
Jian-Yi Meng
,
Xiaoyan Xiang
,
Xiaolang Yan
Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput.
IEEE Trans. Very Large Scale Integr. Syst.
25 (2) (2017)
Tao-Tao Zhu
,
Xiaoyan Xiang
,
Chen Chen
,
Jianyi Meng
SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor.
IEICE Electron. Express
14 (8) (2017)
Tao-Tao Zhu
,
Xiaoyan Xiang
,
Chen Chen
,
Jianyi Meng
A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction.
ASICON
(2015)