Yijin Guan

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 20

Top Topics

Service Architecture

Matrix Multiplication

Weight Matrices

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Teng Ma, Zheng Liu, Chengkun Wei, Jialiang Huang, Youwei Zhuo, Haoyu Li, Ning Zhang, Yijin Guan, Dimin Niu, Mingxing Zhang, Tao Ma
HydraRPC: RPC in the CXL Era. USENIX ATC (2024)
Linyong Huang, Zhe Zhang, Shuangchen Li, Dimin Niu, Yijin Guan, Hongzhong Zheng, Yuan Xie
Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network. IEEE Access 10 (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie
Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging. IEEE Access 10 (2022)
Xingchen Li, Zhihang Yuan, Yijin Guan, Guangyu Sun, Tao Zhang, Rongshan Wei, Dimin Niu
Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du, Fei Xue, Yuanwei Fang, Hongzhong Zheng, Yuan Xie
Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network. ISCA (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie
OpSparse: a Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. CoRR (2022)
Qilin Zheng, Xingchen Li, Yijin Guan, Zongwei Wang, Yimao Cai, Yiran Chen, Guangyu Sun, Ru Huang
PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (12) (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie
Accelerating CPU-based Sparse General Matrix Multiplication with Binary Row Merging. CoRR (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie
OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. IEEE Access 10 (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. CoRR (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. ICPADS (2022)
Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie
3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. ISSCC (2022)
Zhe Zhou, Bizhao Shi, Zhe Zhang, Yijin Guan, Guangyu Sun, Guojie Luo
BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices. CoRR (2021)
Zhe Zhou, Bizhao Shi, Zhe Zhang, Yijin Guan, Guangyu Sun, Guojie Luo
BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices. DAC (2021)
Yijin Guan, Guangyu Sun, Zhihang Yuan, Xingchen Li, Ningyi Xu, Shu Chen, Jason Cong, Yuan Xie
Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs. IEEE Trans. Computers 69 (7) (2020)
Zhao Wang, Yijin Guan, Guangyu Sun, Dimin Niu, Yuhao Wang, Hongzhong Zheng, Yinhe Han
GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks. ACA (2020)
Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. FCCM (2017)
Yijin Guan, Zhihang Yuan, Guangyu Sun, Jason Cong
FPGA-based accelerator for long short-term memory recurrent neural networks. ASP-DAC (2017)
Yijin Guan, Ningyi Xu, Chen Zhang, Zhihang Yuan, Jason Cong
Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators. APPT (2017)
Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, Jason Cong
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. FPGA (2015)