Lide Duan

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 17

Top Topics

Visual Classification

Memory Management

Energy Efficiency

Top Venues

Microprocess. Microsystems

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ACM Trans. Embed. Comput. Syst.

Publications

Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie
3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. ISSCC (2022)
Haoqiang Guo, Lu Peng, Jian Zhang, Fang Qi, Lide Duan
Hardware Accelerator for Adversarial Attacks on Deep Learning Neural Networks. CoRR (2020)
Samuel Irving, Bin Li, Shaoming Chen, Lu Peng, Weihua Zhang, Lide Duan
Computer comparisons in the presence of performance variation. Frontiers Comput. Sci. 14 (1) (2020)
Hao Yan, Hebin R. Cherian, Ethan C. Ahn, Xuehai Qian, Lide Duan
iCELIA: A Full-Stack Framework for STT-MRAM-Based Deep Learning Acceleration. IEEE Trans. Parallel Distributed Syst. 31 (2) (2020)
Armin Haj Aboutalebi, Ethan C. Ahn, Bo Mao, Suzhen Wu, Lide Duan
Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (12) (2019)
Hongyu Liu, Sam Silvestro, Xiaoyin Wang, Lide Duan, Tongping Liu
CSOD: Context-Sensitive Overflow Detection. CGO (2019)
Haoqiang Guo, Lu Peng, Jian Zhang, Fang Qi, Lide Duan
Hardware Accelerator for Adversarial Attacks on Deep Learning Neural Networks. IGSC (2019)
Haoqiang Guo, Lu Peng, Jian Zhang, Fang Qi, Lide Duan
Fooling AI with AI: An Accelerator for Adversarial Attacks on Deep Learning Visual Classification. ASAP (2019)
Hao Yan, Armin Haj Aboutalebi, Lide Duan
Efficient Allocation and Heterogeneous Composition of NVM Crossbar Arrays for Deep Learning Acceleration. IPCCC (2018)
Swanand Mhalagi, Lide Duan, Paul Rad
Designing and evaluating hybrid storage for high performance cloud computing. SysCon (2018)
Bo Mao, Suzhen Wu, Lide Duan
Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (2) (2018)
Hao Yan, Hebin R. Cherian, Ethan C. Ahn, Lide Duan
CELIA: A Device and Architecture Co-Design Framework for STT-MRAM-Based Deep Learning Acceleration. ICS (2018)
Hao Yan, Lei Jiang, Lide Duan, Wei-Ming Lin, Eugene John
FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Armin Haj Aboutalebi, Lide Duan
RAPS: Restore-Aware Policy Selection for STT-MRAM-Based Main Memory under Read Disturbance. ICCD (2017)
Armin Haj Aboutalebi, Lide Duan
Enabling reliable main memory using STT-MRAM via restore-aware memory management: work-in-progress. CASES (2017)
Hao Yan, Ethan C. Ahn, Lide Duan
Enabling NVM-based deep learning acceleration using nonuniform data quantization: work-in-progress. CASES (2017)
Lei Jiang, Wujie Wen, Danghui Wang, Lide Duan
Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read. ASP-DAC (2016)
Lide Duan, Dongyuan Zhan, Justin Hohnerlein
Optimizing Cloud Data Center Energy Efficiency via Dynamic Prediction of CPU Idle Intervals. CLOUD (2015)
Ying Zhang, Lide Duan, Bin Li, Lu Peng, Sadagopan Srinivasan
Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors. Microprocess. Microsystems 39 (4-5) (2015)
Lide Duan, Ying Zhang, Bin Li, Lu Peng
Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules. IEEE Trans. Computers 63 (9) (2014)
Ying Zhang, Lide Duan, Bin Li, Lu Peng, Xin Fu
Design configuration selection for hard-error reliable processors via statistical rules. Microprocess. Microsystems 38 (1) (2014)
Ying Zhang, Lide Duan, Bin Li, Lu Peng, Sadagopan Srinivasan
Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors. ISQED (2014)
Lide Duan, Lu Peng, Bin Li
Predicting Architectural Vulnerability on Multithreaded Processors under Resource Contention and Sharing. IEEE Trans. Dependable Secur. Comput. 10 (2) (2013)
Ying Zhang, Lide Duan, Bin Li, Lu Peng
Optimal microarchitectural design configuration selection for processor hard-error reliability. ISQED (2012)
Lide Duan, Lu Peng, Bin Li
Two-level soft error vulnerability prediction on SMT/CMP architectures. IISWC (2011)
Lide Duan, Ying Zhang, Bin Li, Lu Peng
Universal rules guided design parameter selection for soft error resilient processors. ISPASS (2011)
Ying Zhang, Lu Peng, Wencheng Lu, Lide Duan, Suresh Rai
Expediating IP lookups with reduced power via TBM and SST supernode caching. Comput. Commun. 33 (3) (2010)
Bin Li, Lide Duan, Lu Peng
Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions. IEEE Trans. Computers 59 (5) (2010)
Lide Duan, Bin Li, Lu Peng
Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics. HPCA (2009)
Lu Peng, Wencheng Lu, Lide Duan
Power Efficient IP Lookup with Supernode Caching. GLOBECOM (2007)