Eugene John

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 23

Top Topics

Power Dissipation

Fourier Transform

Transfer Learning

Top Venues

J. Low Power Electron.

Publications

Cory Davis, Patrick M. Stockton, Eugene John
Profiling Analysis for Enhancing the Performance of Graph Neural Networks. ICMLA (2023)
Anshul Jha, Eugene John, Taposh Banerjee
Transfer Learning for COVID-19 and Pneumonia Detection using Chest X-Rays. MWSCAS (2022)
Sayli Siddhasanjay Aphale, Anshul Jha, Eugene John
High Accuracy Arrhythmia Classification using Transfer Learning with Fine-Tuning. UEMCON (2022)
Anshul Jha, Eugene John, Taposh Banerjee
Multi-Class Classification of Dementia from MRI Images Using Transfer Learning. UEMCON (2022)
Cory Davis, Eugene John
Shared Round Core Architecture: A Novel AES Implementation for Implantable Cardiac Devices. MWSCAS (2022)
Wuxia Chen, Taposh Banerjee, Eugene John
A Meta-Transfer Learning Approach to ECG Arrhythmia Detection. EMBC (2022)
Sayli Siddhasanjay Aphale, Eugene John, Taposh Banerjee
ArrhyNet: A High Accuracy Arrhythmia Classification Convolutional Neural Network. MWSCAS (2021)
Taposh Banerjee, Ahmad F. Taha, Eugene John
Robust Quickest Change Detection in Statistically Periodic Processes. ISIT (2021)
Taposh Banerjee, Smruti Padhy, Ahmad F. Taha, Eugene John
Quickest Joint Detection and Classification of Faults in Statistically Periodic Processes. ICASSP (2021)
Taposh Banerjee, Edmond Adib, Ahmad F. Taha, Eugene John
Sequential Methods for Detecting a Change in the Distribution of an Episodic Process. ICASSP (2020)
Kester Leochico, Eugene John
Evaluating Cloud Auto-Scaler Resource Allocation Planning Under High-Performance Computing Workloads. ISPA/BDCloud/SocialCom/SustainCom (2020)
Tarak K. Kodali, Yilin Zhang, Eugene John, Wei-Ming Lin
An Asynchronous High-Performance Approximate Adder with Low-Cost Error Correction. J. Inf. Sci. Eng. 36 (1) (2020)
Safwat Mostafa Noor, Eugene John, Manoj Panday
Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers. IEEE Trans. Very Large Scale Integr. Syst. 27 (4) (2019)
Joseph Whitehouse, Qinzhe Wu, Shuang Song, Eugene John, Andreas Gerstlauer, Lizy K. John
A Study of Core Utilization and Residency in Heterogeneous Smart Phone Architectures. ICPE (2019)
Cory Davis, Alekhya Muthineni, Eugene John
Low-Power Advanced Encryption Standard for Implantable Cardiac Devices. MWSCAS (2019)
Juan Portillo, Eugene John
Using Static Hardware Wrappers to Thwart Hardware Trojans and Code Bugs at Runtime. MWSCAS (2018)
Santosh Koppa, Eugene John
Performance Tradeoffs in the Design of Low-Power SRAM Arrays for Implantable Devices. J. Low Power Electron. 14 (1) (2018)
Gunjan Jha, Eugene John
Performance Analysis of Single-Precision Floating-Point MAC for Deep Learning. MWSCAS (2018)
Hao Yan, Lei Jiang, Lide Duan, Wei-Ming Lin, Eugene John
FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Santosh Koppa, Paromita Syam, Sruthi Nanduru, Eugene John
A quantitative performance analysis of FinFET based multiplier circuits. MWSCAS (2016)
Safwat Mostafa, Eugene John
Reducing Power and Cycle Requirement for Fast Fourier Transform of Electrocardiogram Signals Through Low Level Arithmetic Optimizations for Cardiac Implantable Devices. J. Low Power Electron. 12 (1) (2016)
Juan Portillo, Eugene John, Seetharam Narasimhan
Building trust in 3PIP using asset-based security property verification. VTS (2016)
Santosh Koppa, Manouchehr Mohandesi, Eugene John
An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications. J. Low Power Electron. 12 (4) (2016)
Jiwan Ninglekhu, Ram Krishnan, Eugene John, Manoj Panday
Securing Implantable Cardioverter Defibrillators Using Smartphones. J. Internet Serv. Inf. Secur. 5 (2) (2015)
Savithra Eratne, Pradeep S. Nair, Eugene John
A Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors. J. Low Power Electron. 11 (2) (2015)
Carlos Vazquez, Ram Krishnan, Eugene John
Time Series Forecasting of Cloud Data Center Workloads for Dynamic Resource Provisioning. J. Wirel. Mob. Networks Ubiquitous Comput. Dependable Appl. 6 (3) (2015)
Kathlene Hurt, Eugene John
Analysis of Memory Sensitive SPEC CPU2006 Integer Benchmarks for Big Data Benchmarking. PABS@ICPE (2015)
Kester Leochico, Eugene John
Data retention voltage analysis of various low-power SRAM topologies. MWSCAS (2014)
Nilufar Ferdous, Byeong Kil Lee, Eugene John
Performance enhancement in shared-memory multiprocessors using dynamically classified sharing information. IPCCC (2014)
Yilin Zhang, Marcus Hays, Wei-Ming Lin, Eugene John
Autonomous control of issue queue utilization for simultaneous multi-threading processors. SpringSim (HPS) (2014)
Joseph Whitehouse, Eugene John
Leakage and delay analysis in FinFET array multiplier circuits. MWSCAS (2014)
Prajna Mishra, Eugene John, Wei-Ming Lin
Static noise margin and power dissipation analysis of various SRAM topologies. MWSCAS (2013)
Monobrata Debnath, Wei-Ming Lin, Eugene John
Adaptive instruction dispatching techniques for Simultaneous Multi-Threading (SMT) processors. Comput. Electr. Eng. 38 (6) (2012)
Jie Luo, Kathlene Morales, Byeong Kil Lee, Eugene John, Young Kyu Choi
Performance-sensitivity and performance-similarity based workload reduction. IPCCC (2012)
Savithra Eratne, Eugene John, Byeong Kil Lee
Reducing thermal hotspots in microprocessors with expanded component sizing. MWSCAS (2012)
Byeong Kil Lee, Satish Raghunath, Eugene John
Architectural Sensitivity Analysis on Network Workloads. CDES (2010)
Savithra Eratne, Claudia Romo, Eugene John, Byeong Kil Lee
Leakage and Access Time Tradeoffs for Cache in High Performance Microprocessors. CDES (2010)
Savithra Eratne, Claudia Romo, Eugene John
Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase. CDES (2010)
Ciji Isen, Lizy K. John, Eugene John
A Tale of Two Processors: Revisiting the RISC-CISC Debate. SPEC Benchmark Workshop (2009)
Dhireesha Kudithipudi, Eugene John
Implications of gated-Vss technique on leakage power in embedded caches. Int. J. Embed. Syst. 4 (1) (2009)
Binu P. John, Pradeep S. Nair, Eugene John, Fred W. Hudson
Performance Measurement of Single, Dual and Quad Core Machines Using SPEC CPU2006. CDES (2009)
Pradeep S. Nair, Savithra Eratne, Eugene John
Effects of Register File Organization on Leakage Power Consumption. CDES (2008)
Christopher B. Smith, David R. Mandel, Eugene John
A superscalar simulation employing poisson distributed stalls. Comput. Electr. Eng. 34 (3) (2008)
Savithra Eratne, Sebastian Puthenpurayil, Eugene John
Energy Efficiency of Data Compression with Wavelets. IPCV (2008)
Pradeep S. Nair, Savithra Eratne, Eugene John
Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm. APCCAS (2008)
Savithra Eratne, Sebastian Puthenpurayil, Eugene John
Energy efficient lossless image compression with prediction-based transform. APCCAS (2008)
Pradeep S. Nair, Eugene John
Performance Analysis of an Intel Pentium-4 Based Personal Computer for Multiplke Sequence Alignment. CDES (2007)
Dhireesha Kudithipudi, Eugene John
Static Power Analysis and Estimation in Ternary Content Addressable Memory Cells. J. Low Power Electron. 3 (3) (2007)
Pradeep S. Nair, Dhireesha Kudithipudi, Eugene John, Fred W. Hudson
Performance Analysis of Embedded Applications on a Pentium-4 Based Machine. ESA (2006)
Byeong Kil Lee, Lizy Kurian John, Eugene John
Architectural enhancements for network congestion control applications. IEEE Trans. Very Large Scale Integr. Syst. 14 (6) (2006)
Pradeep S. Nair, Eugene John
Performance of Sequence Alignment Bioinformatics Applications on General Purpose Processors: A Case Study. BIOCOMP (2006)
Dhireesha Kudithipudi, Eugene John
Parametrical characterization of leakage power in embedded system caches using gated-VSS. Circuits, Signals, and Systems (2005)
Dhireesha Kudithipudi, Eugene John
Implementation of Low Power Digital Multipliers using 10 -Transistor Adder Blocks. J. Low Power Electron. 1 (3) (2005)
Byeong Kil Lee, Lizy Kurian John, Eugene John
Architectural Support for Accelerating Congestion Control Applications in Network Processors. ASAP (2005)
Dhireesha Kudithipudi, R. Kotha, Eugene John, Z. Pantic-Tanner
Impact of nanotechnology on the performance of CMOS digital multipliers. Circuits, Signals, and Systems (2004)
Stefan Petko, Dhireesha Kudithipudi, Eugene John
Cache performance of video computation workloads. DCV (2002)
R. Shalem, Lizy Kurian John, Eugene John
A Novel Low Power Energy Recovery Full Adder Cell. Great Lakes Symposium on VLSI (1999)
Eugene John, Fred W. Hudson, Lizy K. John
Hybrid Tree: A Scalable Optoelectronic Interconnection Network for Parallel Computing. HICSS (7) (1998)
Lizyamma Kurian, Daniel Brewer, Eugene John
Design of a highly reconfigurable interconnect for array processors. VLSI Design (1995)