Savithra Eratne

Publication Activity (10 Years)

Years Active: 2008-2015
Publications (10 Years): 0

Top Topics

Multiple Valued

Thermal Conductivity

Scheduling Algorithm

Top Venues

J. Low Power Electron.

Publications

Savithra Eratne, Pradeep S. Nair, Eugene John
A Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors. J. Low Power Electron. 11 (2) (2015)
Pradeep S. Nair, Savithra Eratne, Eugene B. John
Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance. J. Low Power Electron. 8 (4) (2012)
Savithra Eratne, Eugene John, Byeong Kil Lee
Reducing thermal hotspots in microprocessors with expanded component sizing. MWSCAS (2012)
Savithra Eratne, Claudia Romo, Eugene John, Byeong Kil Lee
Leakage and Access Time Tradeoffs for Cache in High Performance Microprocessors. CDES (2010)
Savithra Eratne, Claudia Romo, Eugene John
Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase. CDES (2010)
Pradeep S. Nair, Savithra Eratne, Eugene John
Effects of Register File Organization on Leakage Power Consumption. CDES (2008)
Savithra Eratne, Sebastian Puthenpurayil, Eugene John
Energy Efficiency of Data Compression with Wavelets. IPCV (2008)
Pradeep S. Nair, Savithra Eratne, Eugene John
Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm. APCCAS (2008)
Savithra Eratne, Sebastian Puthenpurayil, Eugene John
Energy efficient lossless image compression with prediction-based transform. APCCAS (2008)