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A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator.

Sai Manoj P. D.Jie LinShikai ZhuYingying YinXu LiuXiwei HuangChongshen SongWenqi ZhangMei YanZhiyi YuHao Yu
Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2017)
Keyphrases
  • network on chip
  • multi processor
  • high speed
  • data transfer
  • power dissipation
  • routing algorithm
  • design methodology
  • computer systems
  • network traffic
  • network simulator