Login / Signup
Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style.
Wanyuan Pan
Yihe Yu
Chengcheng Tang
Ningyuan Yin
Zhiyi Yu
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2024)
Keyphrases
</>
low power
high speed
low cost
power consumption
logic circuits
single chip
high power
delay insensitive
digital signal processing
wireless transmission
vlsi architecture
low power consumption
vlsi circuits
cmos technology
mixed signal
power dissipation
propositional logic
gate array