Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks.
Zhibin XiaoBevan M. BaasPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2014)
Keyphrases
- high speed
- single chip
- functional verification
- network topologies
- social networks
- low cost
- ibm power processor
- processor core
- low power
- high bandwidth
- chip design
- complex networks
- fully connected
- ibm eservertm
- real time
- clock frequency
- multithreading
- shape representation
- shape analysis
- network structure
- input output
- power dissipation
- arbitrary shape
- topological features
- high density
- random access memory
- ibm zenterprise
- end to end
- shape model