Robert T. Golla

Publication Activity (10 Years)

Years Active: 1994-2016
Publications (10 Years): 1

Top Topics

Shared Memory Multiprocessors

Ibm Power Processor

Top Venues

IEEE J. Solid State Circuits

Publications

Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa
SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. IEEE J. Solid State Circuits 51 (1) (2016)
Jinuk Luke Shin, Robert T. Golla, Hongping Penny Li, Sudesna Dash, Youngmoon Choi, Alan P. Smith, Harikaran Sathianathan, Mayur Joshi, Heechoul Park, Mohamed Elgebaly, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Mary Jo Doherty, Greg Grohoski, Curtis McAllister
The Next Generation 64b SPARC Core in a T4 SoC Processor. IEEE J. Solid State Circuits 48 (1) (2013)
Manish Shah, Robert T. Golla, Greg Grohoski, Paul J. Jordan, Jama Barreh, Jeffrey Brooks, Mark Greenberg, Gideon Levinsky, Mark Luttrell, Christopher Olson, Zeid Samoail, Matt Smittle, Thomas A. Ziaja
Sparc T4: A Dynamically Threaded Server-on-a-Chip. IEEE Micro 32 (2) (2012)
Jinuk Luke Shin, Heechoul Park, Hongping Penny Li, Alan P. Smith, Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Robert T. Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister
The next-generation 64b SPARC core in a T4 SoC processor. ISSCC (2012)
Robert T. Golla, Paul J. Jordan
T4: A highly threaded server-on-a-chip with native support for heterogeneous computing. Hot Chips Symposium (2011)
Jama Barreh, Robert T. Golla, L. Baba Arimilli, Paul J. Jordan
POWER2 instruction cache unit. IBM J. Res. Dev. 38 (5) (1994)