SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.
Georgios K. KonstadinidisHongping Penny LiFrancis SchumacherVenkatram KrishnaswamyHoyeol ChoSudesna DashRobert P. MasleidChaoyang ZhengYuanjung David LinPaul LoewensteinHeechoul ParkVijay SrinivasanDawei HuangChangku HwangWenjay HsuCurtis McAllisterJeffrey BrooksHa PhamSebastian TurullolsYifan YangGongRobert T. GollaAlan P. SmithAli VahidsafaPublished in: IEEE J. Solid State Circuits (2016)
Keyphrases
- dynamic random access memory
- processor core
- memory subsystem
- cache misses
- embedded processors
- query processing
- memory hierarchy
- silicon on insulator
- times faster
- multithreading
- shared memory multiprocessor
- database workloads
- data structure
- single chip
- main memory
- memory access
- high speed
- shared memory multiprocessors
- ibm power processor
- low cost
- hit rate
- distributed memory
- low power
- parallel processing
- database systems