Charles Njinda

Publication Activity (10 Years)

Years Active: 1991-2004
Publications (10 Years): 0

Publications

Charles Njinda
A Hierarchical DFT Architecture for Chip, Board and System Test/Debug. ITC (2004)
Rajesh Raina, Charles Njinda, Robert F. Molyneaux
How Seriously Do You Take Your Possible-Detect Faults? ITC (1997)
Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh
Efficient Testing of Clock Regenerator Circuits in Scan Designs. DAC (1997)
Charles Njinda, Neeraj Kaul
Performance Driven BIST Technique for Random Logic. ITC (1995)
Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
SWiTEST: a switch level test generation system for CMOS combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (5) (1994)
Ishwar Parulkar, Melvin A. Breuer, Charles Njinda
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. DAC (1994)
Sen-Pin Lin, Charles Njinda, Melvin A. Breuer
Generating a family of testable designs using the BILBO methodology. J. Electron. Test. 4 (1) (1993)
Sridhar Narayanan, Charles Njinda, Melvin A. Breuer
Optimal Sequencing of Scan Registers. ITC (1992)
Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. DAC (1992)
Sridhar Narayanan, Charles Njinda, Rajesh Gupta, Melvin A. Breuer
SIESTA: a multi-facet scan design system. EURO-DAC (1992)
Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer
Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. ICCAD (1991)
Sen-Pin Lin, Charles Njinda, Melvin A. Breuer
A Systematic Approach for Designing Testable VLSI Circuits. ICCAD (1991)
Rajagopalan Srinivasan, Charles Njinda, Melvin A. Breuer
A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing. VTS (1991)