Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor.
Georgios K. KonstadinidisMarc TremblayShailender ChaudhryMamun RashidPeter F. LaiYukio OtaguroYannis OrginosSudhendra ParampalliMark SteigerwaldShriram GundalaRambabu PyapaliLeonard RarickIlyas ElkinYuefei GeIshwar ParulkarPublished in: IEEE J. Solid State Circuits (2009)
Keyphrases
- multithreading
- parallel computing
- computational power
- highly efficient
- distributed memory
- multi core processors
- coarse grained
- shared memory
- parallel architecture
- memory efficient
- data partitioning
- vlsi implementation
- cmos technology
- computer architecture
- parallel implementation
- message passing
- single layer
- memory management
- fine grained
- motion estimation
- database systems