Verification and Synthesis of Clock-Gated Circuits.
Yu-Yun DaiRobert K. BraytonPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2019)
Keyphrases
- high speed
- logic synthesis
- analog circuits
- asynchronous circuits
- model checking
- program synthesis
- vlsi circuits
- digital circuits
- formal verification
- neural network
- concurrent systems
- logic circuits
- signature verification
- circuit design
- multi valued
- formal analysis
- face verification
- verification method
- artificial intelligence
- electronic circuits
- delay insensitive
- quantum computing
- learning algorithm
- database
- tunnel diode