Hratch Mangassarian

Publication Activity (10 Years)

Years Active: 2005-2014
Publications (10 Years): 0

Top Topics

Probabilistic Planning

Boolean Satisfiability

Error Tolerance

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Hratch Mangassarian, Bao Le, Andreas G. Veneris
Debugging RTL Using Structural Dominance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (2) (2012)
Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita
On error tolerance and Engineering Change with Partially Programmable Circuits. ASP-DAC (2012)
Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris
Non-solution implications using reverse domination in a modern SAT-based debugging environment. DATE (2012)
Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour
Debugging with dominance: On-the-fly RTL debug solution implications. ICCAD (2011)
Hratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus
Leveraging dominators for preprocessing QBF. DATE (2010)
Hratch Mangassarian, Andreas G. Veneris, Marco Benedetti
Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test. IEEE Trans. Computers 59 (7) (2010)
Marco Benedetti, Hratch Mangassarian
QBF-Based Formal Verification: Experience and Perspectives. J. Satisf. Boolean Model. Comput. 5 (1-4) (2008)
Brian Keng, Hratch Mangassarian, Andreas G. Veneris
A succinct memory model for automated design debugging. ICCAD (2008)
Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian
Trace Compaction using SAT-based Reachability Analysis. ASP-DAC (2007)
Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. ICCAD (2007)
Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah
Improved Design Debugging Using Maximum Satisfiability. FMCAD (2007)
Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE (2007)
Hratch Mangassarian, Hassan Artail
A general framework for subjective information extraction from unstructured English text. Data Knowl. Eng. 62 (2) (2007)
Hratch Mangassarian, Mohab Anis
On Statistical Timing Analysis with Inter- and Intra-Die Variations. DATE (2005)