Chasing Minimal Inductive Validity Cores in Hardware Model Checking.
Ryan BerryhillAndreas G. VenerisPublished in: FMCAD (2019)
Keyphrases
- model checking
- temporal logic
- model checker
- finite state
- formal verification
- symbolic model checking
- temporal properties
- formal specification
- partial order reduction
- automated verification
- finite state machines
- verification method
- formal methods
- timed automata
- bounded model checking
- reachability analysis
- process algebra
- pspace complete
- computation tree logic
- concurrent systems
- embedded systems
- processor core
- epistemic logic
- reactive systems
- knowledge representation
- linear temporal logic
- asynchronous circuits
- artificial intelligence
- satisfiability problem
- multi agent systems