Khaled R. Heloue

Publication Activity (10 Years)

Years Active: 2005-2012
Publications (10 Years): 0

Top Topics

Computationally Efficient

Motion Compensation

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Khaled R. Heloue, Sari Onaissi, Farid N. Najm
Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (4) (2012)
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
Clock skew optimization via wiresizing for timing sign-off covering all process corners. DAC (2009)
Khaled R. Heloue, Navid Azizi, Farid N. Najm
Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (6) (2009)
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
PSTA-based branch and bound approach to the silicon speedpath isolation problem. ICCAD (2009)
Khaled R. Heloue, Chandramouli V. Kashyap, Farid N. Najm
Quantifying robustness metrics in parameterized static timing analysis. ICCAD (2009)
Khaled R. Heloue, Sari Onaissi, Farid N. Najm
Efficient block-based parameterized timing analysis covering all potentially critical paths. ICCAD (2008)
Khaled R. Heloue, Farid N. Najm
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (10) (2008)
Khaled R. Heloue, Farid N. Najm
Parameterized timing analysis with general delay models and arbitrary variation sources. DAC (2008)
Khaled R. Heloue, Navid Azizi, Farid N. Najm
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. DAC (2007)
Khaled R. Heloue, Farid N. Najm
Statistical timing analysis with two-sided constraints. ICCAD (2005)