Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA.
Ghizlane Lhairech-LebretonPhilippe CoussyEric MartinPublished in: FPL (2010)
Keyphrases
- low power
- high speed
- power consumption
- low power consumption
- single chip
- high level synthesis
- gate array
- low cost
- power reduction
- digital signal processing
- vlsi architecture
- cmos technology
- logic circuits
- power saving
- parallel architecture
- ultra low power
- real time
- wireless transmission
- design process
- high power
- energy efficiency
- mixed signal
- vlsi circuits
- cmos image sensor
- nm technology
- computer aided
- markov random field
- processing capabilities
- power dissipation