Nathalie Julien

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 5

Top Topics

Activities Of Daily Living

Distributed Architecture

Intelligent User Interfaces

Top Venues

Publications

Aurélian Houé, Cédric Seguin, Florent Frizon de Lamotte, Nathalie Julien, Willy Allègre
Modular and Distributed Architecture Using an Embedded Digital Twin for Adaptation of Assistive Technologies. SOHOMA (2023)
Abbas Ramadan, Florent Frizon De Lamotte, Nathalie Julien
Digital Twin Architecture for Ambient Assisted Living. SOHOMA (2023)
Fatemeh Taei, Mohammed Adel Hamzaoui, Nathalie Julien
CODIT 2023 Modeling of Smart Batteries for the Realization of a Digital Twin Prototype. CoDIT (2023)
Nathalie Julien, Mohammed Adel Hamzaoui
Integrating Lean Data and Digital Sobriety in Digital Twins Through Dynamic Accuracy Management. SOHOMA (2022)
Nathalie Julien, Eric Martin
Typology of Manufacturing Digital Twins: A First Step Towards a Deployment Methodology. SOHOMA (2021)
Van-Trinh Hoang, Nathalie Julien, Pascal Berruet
Design under constraints of availability and energy for sensor node in wireless sensor network. DASIP (2012)
Nicolas Ferry, Sylvain Ducloyer, Nathalie Julien, Dominique Jutel
Power/Energy Estimator for Designing WSN Nodes with Ambient Energy Harvesting Feature. EURASIP J. Embed. Syst. 2011 (2011)
Nicolas Ferry, Sylvain Ducloyer, Nathalie Julien, Dominique Jutel
Energy Estimator for Weather Forecasts Dynamic Power Management of Wireless Sensor Networks. PATMOS (2011)
Ludovic Barrandon, Thierry Capitaine, Loïc Lagadec, Nathalie Julien, Christophe Moy, Thierry Monédière
Virtual SoPC rad-hardening for satellite applications. ReCoSoC (2010)
Eric Senn, David Monnereau, André Rossi, Nathalie Julien
Using Integer Linear Programming in Test-bench Generation for Evaluating Communication Processors. DSD (2009)
Antoine Courtay, Olivier Sentieys, Johann Laurent, Nathalie Julien
High-Level Interconnect Delay and Power Estimation. J. Low Power Electron. 4 (1) (2008)
Antoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses. PATMOS (2008)
Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
Estimation et optimisation de la consommation des mémoires. Tech. Sci. Informatiques 27 (1-2) (2008)
Johann Laurent, Eric Senn, Nathalie Julien
Méthodes et outils d'estimation de la consommation de code embarqué sur processeur. Tech. Sci. Informatiques 26 (5) (2007)
Eric Senn, Nathalie Julien, David Elléouet, Yannig Savary, Nabil Abdelli
Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design. ReCoSoC (2006)
Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin
Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power CoRR (2006)
Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
Memory Aware High-Level Synthesis for Embedded Systems CoRR (2006)
Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin
A Memory Aware High Level Synthesis Too CoRR (2006)
David Elléouet, Yannig Savary, Nathalie Julien
An FPGA Power Aware Design Flow. PATMOS (2006)
David Elléouet, Nathalie Julien, Dominique Houzet
A high level SoC power estimation based on IP modeling. IPDPS (2006)
Nathalie Julien, Johann Laurent, Eric Senn, David Elléouet, Yannig Savary, Nabil Abdelli, J. Ktari
Power/Energy Estimation in SoCs by Multi-Level Parametric Modeling. ReCoSoC (2005)
Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin
SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications. EURASIP J. Adv. Signal Process. 2005 (16) (2005)
Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
A memory aware behavioral synthesis tool for real-time VLSI circuits. ACM Great Lakes Symposium on VLSI (2004)
David Elléouet, Nathalie Julien, Dominique Houzet, Jean-Gabriel Cousin, Eric Martin
Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. DSD (2004)
Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin
Memory accesses management during high level synthesis. CODES+ISSS (2004)
Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
Memory Aware HLS and the Implementation of Ageing Vectors. DSD (2004)
Nathalie Julien
Panorama des outils d'analyse et d'optimisation de la consommation dans les systèmes sur puce (SoC). Ann. des Télécommunications 59 (7-8) (2004)
Johann Laurent, Nathalie Julien, Eric Senn, Eric Martin
Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors. DATE (2004)
Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level. PATMOS (2004)
Florian Marteil, Nathalie Julien, Eric Senn, Eric Martin
A Complete Methodology for Memory Optimization in DSP Applications. DSD (2004)
Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
A Memory Aware High Level Synthesis Tool . ISVLSI (2004)
Nathalie Julien, S. Gailhard, Eric Martin
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT. J. VLSI Signal Process. 35 (2) (2003)
Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin
Power Consumption Modeling and Characterization of the TI C6201. IEEE Micro 23 (5) (2003)
Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin
Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor. ISHPC (2002)
Eric Senn, Nathalie Julien, Johann Laurent, Eric Martin
Power Consumption Estimation of a C Program for Data-Intensive Applications. PATMOS (2002)
S. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures. Great Lakes Symposium on VLSI (1999)
Stephane Gailhard, Nathalie Julien, Eric Martin
Adaptive filters implementation performances under power dissipation constraint. EUSIPCO (1998)
S. Gailhard, Nathalie Julien, Jean-Philippe Diguet, Eric Martin
How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs. Great Lakes Symposium on VLSI (1998)