Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach.
Tiankai SuAtif YasinSébastien PillementMaciej J. CiesielskiPublished in: ISVLSI (2020)
Keyphrases
- formal verification
- model checking
- model checker
- bounded model checking
- symbolic model checking
- automated verification
- program slicing
- high speed
- analog circuits
- functional verification
- expert systems
- arithmetic operations
- electronic circuits
- asynchronous circuits
- knowledge base
- floating point
- computer systems
- web services