Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis.

Tiankai Su Cunxi Yu Atif Yasin Maciej J. Ciesielski

Published in: ISVLSI (2017)

Keyphrases

formal verification
model checking
model checker
automated verification
symbolic model checking
bounded model checking
program synthesis
texture synthesis
functional verification
program slicing
algebraic structure
test set
temporal logic