Daniel Chillet

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 17

Top Topics

Top Venues

SiPhotonics@HiPEAC

Publications

Wilfread Guillemé, Angeliki Kritikakou, Youri Helen, Cédric Killian, Daniel Chillet
VANDOR: Mitigating SEUs into Quantized Neural Networks. IOLTS (2024)
Léo Pradels, Silviu-Ioan Filip, Olivier Sentieys, Daniel Chillet, Thibaut Le Calloch
FPGA-based CNN Acceleration using Pattern-Aware Pruning. AICAS (2024)
Ibrahim Krayem, Joel Ortiz Sosa, Cédric Killian, Daniel Chillet
Analytical Model for Performance Evaluation of Token-Passing-Based WiNoCs. IEEE Des. Test 40 (6) (2023)
Jaechul Lee, Cédric Killian, Sébastien Le Beux, Daniel Chillet
Distance-aware Approximate Nanophotonic Interconnect. ACM Trans. Design Autom. Electr. Syst. 27 (2) (2022)
Ibrahim Krayem, Romain Mercier, Cédric Killian, Angeliki Kritikakou, Daniel Chillet
Data and Fault Aware Routing Algorithm for NoC Based Approximate Computing. NANOARCH (2022)
Romain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet
BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Romain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet
A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation Efficiency. DFT (2021)
Romain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet
Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-an-Chip Architecture. ICCD (2020)
Aymen Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet
Energy-Efficient Scheduling of Real-Time Tasks in Reconfigurable Homogeneous Multicore Platforms. IEEE Trans. Syst. Man Cybern. Syst. 50 (12) (2020)
Jaechul Lee, Cédric Killian, Sébastien Le Beux, Daniel Chillet
Approximate nanophotonic interconnects. NOCS (2019)
Jiating Luo, Van-Dung Pham, Cédric Killian, Daniel Chillet, Ian O'Connor, Olivier Sentieys, Sébastien Le Beux
Run-Time management of energy-performance trade-off in Optical Network-on-Chip. DCIS (2018)
Aymen Gammoudi, Daniel Chillet, Mohamed Khalgui, Adel Benzina
Mapping of Periodic Tasks in Reconfigurable Heterogeneous Multi-core Platforms. ENASE (2018)
Jiating Luo, Cédric Killian, Sébastien Le Beux, Daniel Chillet, Olivier Sentieys, Ian O'Connor
Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects. ACM J. Emerg. Technol. Comput. Syst. 14 (2) (2018)
Jiating Luo, A. Elantably, Van-Dung Pham, Cédric Killian, Daniel Chillet, Sébastien Le Beux, Olivier Sentieys, Ian O'Connor
Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC. DATE (2017)
Cédric Killian, Daniel Chillet, Sébastien Le Beux, Van-Dung Pham, Olivier Sentieys, Ian O'Connor
Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques. DAC (2017)
Robin Bonamy, Sébastien Bilavarn, Daniel Chillet, Olivier Sentieys
Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems. J. Low Power Electron. 12 (3) (2016)
Aymen Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet
Real-Time Scheduling of Reconfigurable Battery-Powered Multi-Core Platforms. ICTAI (2016)
Johanna Sepúlveda, Sébastien Le Beux, Jiating Luo, Cédric Killian, Daniel Chillet, Hui Li, Ian O'Connor, Olivier Sentieys
Communication Aware Design Method for Optical Network-on-Chip. MCSoC (2015)
Aymen Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet
New Pack Oriented Solutions for Energy-Aware Feasible Adaptive Real-Time Systems. SoMeT (2015)
Jiating Luo, Cédric Killian, Sébastien Le Beux, Daniel Chillet, Hui Li, Ian O'Connor, Olivier Sentieys
Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip. SiPhotonics@HiPEAC (2015)
Daniel Chillet, Michael Hübner
Special issue on design and architectures of real-time image processing in embedded systems. J. Real Time Image Process. 9 (1) (2014)
Robin Bonamy, Sébastien Bilavarn, Daniel Chillet, Olivier Sentieys
Power consumption models for the use of dynamic and partial reconfiguration. Microprocess. Microsystems 38 (8) (2014)
Quang-Hai Khuat, Daniel Chillet, Michael Hübner
Considering reconfiguration overhead in scheduling of dependent tasks on 2D reconfigurable FPGA. AHS (2014)
Quang-Hai Khuat, Daniel Chillet, Michael Hübner
Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC. ReConFig (2014)
Rajhans Singh, Daniel Chillet
Intrinsic Fault Tolerance of Hopfield Artificial Neural Network Model for Task Scheduling Technique in SoC. IJCCI (NCTA) (2014)
Quang-Hai Khuat, Daniel Chillet
Communication cost reduction for hardware tasks placed on homogeneous reconfigurable resource. DASIP (2013)
Quang-Hai Khuat, Quang-Hoa Le, Daniel Chillet, Sébastien Pillement
Spatio-temporal scheduling for 3D reconfigurable & multiprocessor architecture. IDT (2013)
Rabie Ben Atitallah, Eric Senn, Daniel Chillet, Mickael Lanoe, Dominique Blouin
An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC. IEEE Trans. Ind. Informatics 9 (1) (2013)
Eric Senn, Daniel Chillet, Olivier Zendra, Cécile Belleudy, Sébastien Bilavarn, Rabie Ben Atitallah, Christian Samoyeau, A. Fritsch
Open-People: Open Power and Energy Optimization PLatform and Estimator. DSD (2012)
Eric Senn, Daniel Chillet, Olivier Zendra, Cécile Belleudy, Rabie Ben Atitallah, A. Fritsch, Christian Samoyeau
Open-people: An open platform for estimation and optimizations of energy consumption. DASIP (2012)
Robin Bonamy, Hung-Manh Pham, Sébastien Pillement, Daniel Chillet
UPaRC - Ultra-fast power-aware reconfiguration controller. DATE (2012)
Robin Bonamy, Daniel Chillet, Sébastien Bilavarn, Olivier Sentieys
Power consumption model for partial and dynamic reconfiguration. ReConFig (2012)
Surya Narayanan, Ludovic Devaux, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources. VLSI-SoC (2011)
Surya Narayanan, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis
Hardware OS Communication Service and Dynamic Memory Management for RSoCs. ReConFig (2011)
Dominique Blouin, Daniel Chillet, Eric Senn, Sébastien Bilavarn, Robin Bonamy, Christian Samoyeau
AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC. Int. J. Reconfigurable Comput. 2011 (2011)
Robin Bonamy, Daniel Chillet, Olivier Sentieys, Sébastien Bilavarn
Towards a power and energy efficient use of partial dynamic reconfiguration. ReCoSoC (2011)
Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
Parallel Evaluation of Hopfield Neural Networks. IJCCI (NCTA) (2011)
Daniel Chillet, Antoine Eiche, Sébastien Pillement, Olivier Sentieys
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network. J. Syst. Archit. 57 (4) (2011)
Robin Bonamy, Daniel Chillet, Olivier Sentieys, Sébastien Bilavarn
Parallelism Level Impact on Energy Consumption in Reconfigurable Devices. SIGARCH Comput. Archit. News 39 (4) (2011)
Daniel Chillet
Open-People: Open Power and Energy Optimization PLatform and Estimator. PATMOS (2010)
Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny
R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip. ReConFig (2010)
Ludovic Devaux, Sana Ben Sassi, Sébastien Pillement, Daniel Chillet, Didier Demigny
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures. Int. J. Reconfigurable Comput. 2010 (2010)
Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
Task placement for dynamic and partial reconfigurable architecture. DASIP (2010)
Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny
Mesh and Fat-Tree comparison for dynamically reconfigurable applications. ReCoSoC (2010)
Sébastien Pillement, Daniel Chillet, Yaset Oliva, Jean-Christophe Prévotet
High-Level Exploration for Dynamic Reconfiguration Management. ERSA (2009)
Benoît Miramond, Emmanuel Huck, François Verdier, Mohamed El Amine Benkhelifa, Bertrand Granado, Thomas LeFebvre, Mehdi Aïchouch, Jean-Christophe Prévotet, Yaset Oliva, Daniel Chillet, Sébastien Pillement
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms. Int. J. Reconfigurable Comput. 2009 (2009)
Daniel Chillet, Raphaël David, Erwan Grâce, Olivier Sentieys
Structure mémoire reconfigurable. Vers une structure de stockage faible consommation. Tech. Sci. Informatiques 27 (1-2) (2008)
Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Bertrand Granado, Emmanuel Huck, Benoît Miramond, François Verdier, Daniel Chillet, Sébastien Pillement
A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. ReConFig (2008)
Imene Benkermi, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
Hardware task scheduling for heterogeneous soc architectures. EUSIPCO (2007)
Daniel Chillet, Sébastien Pillement, Olivier Sentieys
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. IJCNN (2007)
Daniel Ménard, Daniel Chillet, Olivier Sentieys
Floating-to-Fixed-Point Conversion for Digital Signal Processors. EURASIP J. Adv. Signal Process. 2006 (2006)
Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys
Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC (2005)
François Verdier, Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Daniel Chillet, Sébastien Pillement
Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. ReCoSoC (2005)
Daniel Ménard, Taofik Saïdi, Daniel Chillet, Olivier Sentieys
Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe. Tech. Sci. Informatiques 22 (6) (2003)
Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
Mapping future generation mobile telecommunication applications on a dynamically reconfigurable arcidtecture. ICASSP (2002)
Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. IPDPS (2002)
Daniel Ménard, Daniel Chillet, François Charot, Olivier Sentieys
Automatic floating-point to fixed-point conversion for DSP code generation. CASES (2002)
Sébastien Pillement, Daniel Chillet, Olivier Sentieys
Behavioral IP Specification and Integration Framework for High-Level Design Reuse. ISQED (2002)
Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
A Compilation Framework for a Dynamically Reconfigurable Architecture. FPL (2002)
Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. VLSI-SOC (2001)
Jean-Gabriel Cousin, Olivier Sentieys, Daniel Chillet
Multi-algorithm ASIP synthesis and power estimation for DSP applications. ISCAS (2000)
Hélène Dubois, Olivier Sentieys, Daniel Chillet, Jean Luc Philippe
Teaching hardware/software system codesign using CAD tools: a case study in image synthesis. IEEE Trans. Educ. 43 (3) (2000)
Jean-Philippe Diguet, Daniel Chillet, Olivier Sentieys
A Framework for High Level Estimations of Signal Processing VLSI Implementations. J. VLSI Signal Process. 25 (3) (2000)
J. O. Dedou, Daniel Chillet, Olivier Sentieys
Behavioral synthesis of asynchronous systems: a methodology. ISCAS (6) (1999)
Daniel Chillet, Olivier Sentieys, Michel Corazza
Memory Unit Design for Real Time DSP Applications. Great Lakes Symposium on VLSI (1999)
J. Okito Dedou, Daniel Chillet, Olivier Sentieys
Asynchronous timing model for high-level synthesis of DSP applications. EUSIPCO (1998)
Jean-Philippe Diguet, Olivier Sentieys, Daniel Chillet, Jean Luc Philippe
VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters. ICASSP (1997)
Jean Luc Philippe, Daniel Chillet, Olivier Sentieys, Jean-Philippe Diguet
Memory aspects in signal processing and HLS tool: Some results. EUSIPCO (1996)