A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking.
Martin CochetSylvain ClercMehdi NaceurPierre SchambergerDamien CroainJean-Luc AutranPhilippe RochePublished in: ISCAS (2016)
Keyphrases
- low power
- open loop
- closed loop
- low cost
- high speed
- cmos technology
- power consumption
- silicon on insulator
- control system
- power dissipation
- nm technology
- low power consumption
- feedback control
- power reduction
- inverted pendulum
- logic circuits
- digital signal processing
- gate array
- floating point
- control scheme
- image sensor
- stability analysis
- evolutionary algorithm
- power management
- real time