A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells.

Ludovic Moreau Rémi Dekimpe David Bol

Published in: ISCAS (2019)

Keyphrases

power dissipation
clock gating
cmos technology
flip flops
power consumption
low power
nm technology
power reduction
digital signal processing
low cost
high speed
design methodology
low voltage
finite state machines
power saving
energy efficiency
computer vision
silicon on insulator