Rémi Dekimpe

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 10

Top Topics

Cmos Technology

Pareto Optimality

Top Venues

IEEE Trans. Biomed. Circuits Syst.

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Internet Things J.

Publications

Rémi Dekimpe, David Bol
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (8) (2024)
Marco Gonzalez, Pengcheng Xu, Rémi Dekimpe, Maxime Schramme, Ivan Stupia, Thibault Pirson, David Bol
Technical and Ecological Limits of 2.45-GHz Wireless Power Transfer for Battery-Less Sensors. IEEE Internet Things J. 10 (17) (2023)
Rémi Dekimpe, David Bol
ECG Arrhythmia Classification on an Ultra-Low-Power Microcontroller. IEEE Trans. Biomed. Circuits Syst. 16 (3) (2022)
Rémi Dekimpe, David Bol
Mixed-Signal Compensation of Tripolar Cuff Electrode Imbalance in a Low-Noise ENG Analog Front-End. ESSCIRC (2022)
David Bol, Maxime Schramme, Ludovic Moreau, Pengcheng Xu, Rémi Dekimpe, Roghayeh Saeidi, Thomas Haine, Charlotte Frenkel, Denis Flandre
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. IEEE J. Solid State Circuits 56 (7) (2021)
Rémi Dekimpe, Maxime Schramme, Martin Lefebvre, Adrian Kneip, Roghayeh Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, David Bol
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management. VLSI Circuits (2021)
David Bol, Thibault Pirson, Rémi Dekimpe
Moore's Law and ICT Innovation in the Anthropocene. DATE (2021)
Martin Lefebvre, Ludovic Moreau, Rémi Dekimpe, David Bol
A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection. ISSCC (2021)
Rémi Dekimpe, David Bol
A Configurable ULP Instrumentation Amplifier With Pareto-Optimal Power-Noise Trade-Off Achieving 1.93 NEF in 65nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68 (7) (2021)
Ludovic Moreau, Rémi Dekimpe, David Bol
A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells. ISCAS (2019)