SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode.

David BolMaxime SchrammeLudovic MoreauPengcheng XuRémi DekimpeRoghayeh SaeidiThomas HaineCharlotte FrenkelDenis Flandre
Published in: IEEE J. Solid State Circuits (2021)
Keyphrases
  • knowledge base
  • power consumption
  • genetic algorithm
  • information systems
  • data structure
  • cmos technology
  • mixed mode