A Configurable ULP Instrumentation Amplifier With Pareto-Optimal Power-Noise Trade-Off Achieving 1.93 NEF in 65nm CMOS.
Rémi DekimpeDavid BolPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2021)
Keyphrases
- pareto optimal
- trade off
- power consumption
- high power
- silicon on insulator
- multi objective
- conflicting objectives
- low power
- multiple objectives
- power supply
- multi objective optimization
- cmos technology
- nash equilibrium
- pareto optimality
- nm technology
- multi issue negotiation
- pareto optimal set
- nsga ii
- high speed
- social welfare
- pareto optimal solutions
- low cost
- optimal solution
- evolutionary algorithm
- ibm power processor
- genetic algorithm
- dynamic range
- signal to noise ratio
- optimization algorithm
- multiobjective optimization
- tabu search
- particle swarm optimization
- objective function