Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI.
Cecilia GimenoDenis FlandreDavid BolPublished in: LASCAS (2018)
Keyphrases
- low power
- power consumption
- high speed
- cmos technology
- nm technology
- low cost
- energy dissipation
- power reduction
- high power
- single chip
- vlsi circuits
- power saving
- digital signal processing
- vlsi architecture
- wireless transmission
- logic circuits
- rate allocation
- mixed signal
- low voltage
- real time
- gate array
- signal processing