Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits.
François StasDavid BolPublished in: ISCAS (2017)
Keyphrases
- low power
- power dissipation
- cmos technology
- high speed
- power consumption
- flip flops
- low cost
- logic circuits
- vlsi circuits
- power reduction
- delay insensitive
- high power
- single chip
- image sensor
- gate array
- low power consumption
- digital signal processing
- low voltage
- mixed signal
- asynchronous circuits
- computer vision
- wireless transmission
- signal processor