An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation.
Thomas HaineQuoc-Khoi NguyenFrançois StasLudovic MoreauDenis FlandreDavid BolPublished in: ESSCIRC (2017)
Keyphrases
- nm technology
- power consumption
- cmos technology
- random access memory
- energy efficiency
- low power
- energy saving
- low voltage
- high speed
- embedded dram
- power management
- power dissipation
- low cost
- power saving
- image sensor
- design considerations
- energy minimization
- mixed signal
- parallel processing
- high density
- random access
- power reduction
- flip flops
- energy consumption
- sensor networks