Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements.
Juan NúñezMaria J. AvedilloJosé M. QuintanaPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2014)
Keyphrases
- fine grained
- coarse grained
- high speed
- logic synthesis
- flip flops
- delay insensitive
- access control
- tightly coupled
- asynchronous circuits
- digital circuits
- data flow
- logic circuits
- data lineage
- massively parallel
- knowledge representation
- data provenance
- belief propagation
- power consumption
- chip design
- parallel algorithm