Maria J. Avedillo

Publication Activity (10 Years)

Years Active: 1990-2023
Publications (10 Years): 9

Top Topics

Power Consumption

Network Externalities

Top Venues

IEEE J. Emerg. Sel. Topics Circuits Syst.

IEEE Trans. Neural Networks Learn. Syst.

Publications

Maria J. Avedillo, Manuel Jiménez Través, Corentin Delacour, Aida Todri-Sanial, Bernabé Linares-Barranco, Juan Núñez
Operating Coupled VO₂-Based Oscillators for Solving Ising Models. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (4) (2023)
Juan Núñez, Maria J. Avedillo, Manuel Jiménez
Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices. SMACD (2023)
Juan Núñez, Simon Thomann, Hussam Amrouch, Maria J. Avedillo
Mitigating the Impact of Variability in NCFET-based Coupled-Oscillator Networks Applications. ICECS 2022 (2022)
Aida Todri-Sanial, Stefania Carapezzi, Corentin Delacour, Madeleine Abernot, Thierry Gil, Elisabetta Corti, Siegfried F. Karg, Juan Núñez, Manuel Jiménez, Maria J. Avedillo, Bernabé Linares-Barranco
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase. IEEE Trans. Neural Networks Learn. Syst. 33 (5) (2022)
Juan Núñez, Maria J. Avedillo
Power and Speed Evaluation of Hyper-FET Circuits. IEEE Access 7 (2019)
Hector J. Quintero, Manuel Jimenez, Maria J. Avedillo, Juan Núñez
Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. SMACD (2018)
Maria J. Avedillo, Juan Núñez
Impact of the RT-level architecture on the power performance of tunnel transistor circuits. Int. J. Circuit Theory Appl. 46 (3) (2018)
Juan Núñez, Maria J. Avedillo
Exploring logic architectures suitable for TFETs devices. ISCAS (2017)
Maria J. Avedillo, Juan Núñez
Impact of pipeline in the power performance of tunnel transistor circuits. PATMOS (2016)
Juan Núñez, Maria J. Avedillo, Hector J. Quintero
DOE based high-performance gate-level pipelines. PATMOS (2014)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Novel Dynamic Gate Topology for Superpipelines in DSM Technologies. DSD (2013)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Novel pipeline architectures based on Negative Differential Resistance devices. Microelectron. J. 44 (9) (2013)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Compact and Power Efficient MOS-NDR Muller C-Elements. DoCEIS (2012)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Bifurcation diagrams in MOS-NDR frequency divider circuits. ICECS (2012)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications. PATMOS (2012)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Efficient realization of RTD-CMOS logic gates. ACM Great Lakes Symposium on VLSI (2011)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Single phase MOS-NDR mobile networks. ISCAS (2010)
Héctor Pettenghi, Ricardo Chaves, Leonel Sousa, Maria J. Avedillo
+/- k based on threshold logic. VLSI-SoC (2010)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Evaluation of RTD-CMOS Logic Gates. DSD (2010)
José M. Quintana, Maria J. Avedillo, Juan Núñez, Héctor Pettenghi
Operation Limits for RTD-Based MOBILE Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2009)
Juan Núñez, José M. Quintana, Maria J. Avedillo
Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR. ISCAS (2009)
José M. Quintana, Maria J. Avedillo
Analysis of the critical rise time in MOBILE-based circuits. ICECS (2008)
Héctor Pettenghi, Maria J. Avedillo, José M. Quintana
Using multi-threshold threshold gates in RTD-based logic design: A case study. Microelectron. J. 39 (2) (2008)
Héctor Pettenghi, Maria J. Avedillo, José M. Quintana
A novel contribution to the RTD-based threshold logic family. ISCAS (2008)
Juan Núñez, José M. Quintana, Maria J. Avedillo
Limits to a correct operation in RTD-based ternary inverters. ISCAS (2008)
Juan Núñez, José M. Quintana, Maria J. Avedillo
Correct operation in SMOBILE-based quasi-differential quantizers. ECCTD (2007)
Juan Núñez, José M. Quintana, Maria J. Avedillo
A quasi-differential quantizer based on SMOBILE. SBCCI (2007)
Juan Núñez, José M. Quintana, Maria J. Avedillo
Operation limits in RTD-based ternary quantizers. ACM Great Lakes Symposium on VLSI (2007)
Juan Núñez, José M. Quintana, Maria J. Avedillo
Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. ISMVL (2007)
Héctor Pettenghi, Maria J. Avedillo, José M. Quintana
Non Return Mobile Logic Family. ISCAS (2007)
José M. Quintana, Maria J. Avedillo, Juan Núñez
Design Guides for a Correct DC Operation in RTD-based Threshold Gates. DSD (2006)
Maria J. Avedillo, José M. Quintana, Héctor Pettenghi Roldán
Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors. IEEE Trans. Circuits Syst. II Express Briefs (5) (2006)
José M. Quintana, Maria J. Avedillo, Héctor Pettenghi
Self-latching operation limits for MOBILE circuits. ISCAS (2006)
José M. Quintana, Maria J. Avedillo
Analysis of frequency divider RTD circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2005)
Maria J. Avedillo, José M. Quintana, José L. Huertas
Robust frequency divider based on resonant tunneling devices. ISCAS (3) (2005)
Maria J. Avedillo, José M. Quintana, Héctor Pettenghi
Logic Models Supporting the Design of MOBILE-based RTD Circuits. ASAP (2005)
Maria J. Avedillo, José M. Quintana, Raúl Jiménez-Naharro
Pass-transistor based implementations of threshold logic gates for WOS filtering. Microelectron. J. 35 (11) (2004)
José M. Quintana, Maria J. Avedillo, Héctor Pettenghi
Programmable logic gate based on resonant tunnelling devices. ISCAS (3) (2004)
Maria J. Avedillo, José M. Quintana
A Threshold Logic Synthesis Tool for RTD Circuits. DSD (2004)
Maria J. Avedillo, José M. Quintana, Hamid El Alami, Antonio Jiménez-Calderón
A Practical Parallel Architecture for Stacks Filters. J. VLSI Signal Process. 38 (2) (2004)
Valeriu Beiu, José M. Quintana, Maria J. Avedillo
VLSI implementations of threshold logic-a comprehensive survey. IEEE Trans. Neural Networks 14 (5) (2003)
Valeriu Beiu, José M. Quintana, Maria J. Avedillo
Review of Differential Threshold Gate Implementations. Neural Networks and Computational Intelligence (2003)
Valeriu Beiu, Maria J. Avedillo, José M. Quintana
Review of Capacitive Threshold Gate Implementations. ICANN (2003)
Maria J. Avedillo, José M. Quintana, Esther Rodríguez-Villegas
Simple parallel weighted order statistic filter implementations. ISCAS (4) (2002)
Esther Rodríguez-Villegas, José M. Quintana, Maria J. Avedillo, Adoración Rueda
High-speed low-power logic gates using floating gates. ISCAS (5) (2002)
Manuel Martínez, Maria J. Avedillo, José M. Quintana, H. Süß, Manfred Koegst
An Encoding Technique for Low Power CMOS Implementations of Controllers. DATE (2002)
José M. Quintana, Maria J. Avedillo, Esther Rodríguez-Villegas, Adoración Rueda
Threshold-logic-based design of compressors. ICECS (2002)
José M. Quintana, Maria J. Avedillo, José L. Huertas
Simplified Reed-Muller expressions for residue threshold functions. ISCAS (4) (2002)
José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas
Low-power logic styles for full-adder circuits. ICECS (2001)
José M. Quintana, Maria J. Avedillo, José Luis Huertas
Efficient Realization of a Threshold Voter for Self-Purging Redundancy. J. Electron. Test. 17 (1) (2001)
José M. Quintana, Maria J. Avedillo
Reed-Muller descriptions of symmetric functions. ISCAS (4) (2001)
Manfred Koegst, Steffen Rülke, Günter Franke, Maria J. Avedillo
Two-Criterial Constraint-Driven FSM State Encoding for Low Power. DSD (2001)
José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas
Practical low-cost CPL implementations threshold logic functions. ACM Great Lakes Symposium on VLSI (2001)
Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda
νMOS-based Sorter for Arithmetic Applications. VLSI Design 2000 (2) (2000)
José M. Quintana, Maria J. Avedillo, Esther Rodríguez-Villegas, Adoración Rueda
Efficient νMOS Realization of Threshold Voters for Self-Purging Redundancy. SBCCI (2000)
Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda
vMOS-based sorters for multiplier implementations. ISCAS (1) (1999)
Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. DATE (1999)
Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas
A Dynamic Model for the State Assignment Problem. DATE (1998)
José M. Quintana, Maria J. Avedillo, Maria P. Parra, José L. Huertas
Optimum PLA folding through boolean satisfiability. ASP-DAC (1995)
Maria J. Avedillo, José M. Quintana, José Luis Huertas
Constrained state assignment of easily testable FSMs. J. Electron. Test. 6 (1) (1995)
Maria J. Avedillo, José M. Quintana, José L. Huertas
Easily Testable PLA-based FSMS. ISCAS (1993)
Maria J. Avedillo, José M. Quintana, José Luis Huertas
A new method for the state reduction of incompletely specified finite sequential machines. EURO-DAC (1990)