Steffen Rülke

Publication Activity (10 Years)

Years Active: 1997-2012
Publications (10 Years): 0

Top Venues

DDECS

Academy of Sciences of the German Democratic Republic, Berlin, Germany (PHD)

Education History

Academy of Sciences of the German Democratic Republic, Berlin, Germany

PHD

Publications

Thilo Vörtler, Steffen Rülke, Petra Hofstedt
Bounded model checking of Contiki applications. DDECS (2012)
Frank Rogin, Rolf Drechsler, Steffen Rülke
Automatic debugging of System-on-a-Chip designs. SoCC (2009)
Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
Advanced verification by automatic property generation. IET Comput. Digit. Tech. 3 (4) (2009)
Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
Automatic Generation of Complex Properties for Hardware Designs. DATE (2008)
Maik Boden, Thomas Fiebig, Markus Reiband, Peter Reichel, Steffen Rülke
GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs. ISVLSI (2008)
Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke
An Integrated SystemC Debugging Environment. FDL (2007)
Maik Boden, Thomas Fiebig, Torsten Meibner, Steffen Rülke, Jürgen Becker
High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs. IPDPS (2007)
Rene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt
A Tailored Design Partitioning Method for Hardware Emulation. IEEE International Workshop on Rapid System Prototyping (2007)
Rene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt
A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator. DSD (2007)
Maik Boden, Steffen Rülke, Jürgen Becker
A high-level target-precise model for designing reconfigurable HW tasks. IPDPS (2006)
Frank Rogin, Erhard Fehlauer, Steffen Rülke, Sebastian Ohnewald, Thomas Berndt
Non-Intrusive High-level SystemC Debugging. FDL (2006)
Maik Boden, Alex Gleich, Steffen Rülke, Ulrich Nageldinger
A Low-Cost Realization of an Adaptable Protocol Processing Unit. IPDPS (2005)
Jörg Schneider, Vincent Kotzsch, Steffen Rülke
Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment. PARELEC (2004)
Maik Boden, Manfred Koegst, José Luis Tiburcio Badía, Steffen Rülke
Cost-Efficient Implementation of Adaptive Finite State Machines. DSD (2004)
Hans-Jürgen Brand, Steffen Rülke, Martin Radetzki
IPQ: IP Qualification for Efficient System Design. ISQED (2004)
Jörg Schneider, Maik Boden, Steffen Rülke
Eine wiederverwendungsgerechte Entwurfsmethodik für rekonfigurierbare SoC-Architekturen. MBMV (2002)
Ronny Frevert, Steffen Rülke, Torsten Schäfer, Frank Dresig
Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement Analysis. DSD (2002)
Maik Boden, Jörg Schneider, Klaus Feske, Steffen Rülke
Enhanced Reusability for SoC-Based HW/SW Co-Design. DSD (2002)
Manfred Koegst, Steffen Rülke, Günter Franke, Maria J. Avedillo
Two-Criterial Constraint-Driven FSM State Encoding for Low Power. DSD (2001)
Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske
Multi-Criterial State Assignment for Low Power FSM Design. EUROMICRO (1998)
Manfred Koegst, Günter Franke, Klaus Feske, Steffen Rülke
Verringerung der Leistungsaufnahme in sequentiellen Schaltungen durch Vorlogik und zweistufige Zustandskodierung. MBMV (1998)
Klaus Feske, Steffen Rülke, Manfred Koegst
FPGA based prototyping using a target driven FSM partitioning strategy. ICECS (1998)
Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske
Low Power Design of FSMs by State Assignment and Disabling Self-Loops. EUROMICRO (1997)

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Publication Activity (10 Years)

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Steffen Rülke