Impact of the RT-level architecture on the power performance of tunnel transistor circuits.

Maria J. Avedillo Juan Núñez

Published in: Int. J. Circuit Theory Appl. (2018)

Keyphrases

high speed
power dissipation
power consumption
low power
real time
higher level
power reduction
power management
network architecture
levels of abstraction
design considerations
neural network
management system
low cost
logic circuits