Login / Signup
Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths.
Victor M. van Santen
Jose M. Gata-Romero
Juan Núñez
Rafael Castro-López
Elisenda Roca
Hussam Amrouch
Published in:
IRPS (2023)
Keyphrases
</>
high speed
asynchronous circuits
chip design
random access memory
single chip
delay insensitive
low cost
logic programming
parallel processing
communication systems
classical logic
neural network
logic programs
design considerations
circuit design
cmos technology