Manuel J. Barragan

Publication Activity (10 Years)

Years Active: 2013-2023
Publications (10 Years): 41

Top Topics

Design Methodology

Feature Selection

Machine Learning

Monte Carlo Simulation

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

J. Electron. Test.

Publications

Dayana A. Pino-Monroy, Patrick Scheer, Mohamed Khalil Bouchoucha, Carlos Galup-Montoro, Manuel J. Barragan, Jean-Michel Fournier, Andreia Cathelin, Sylvain Bourdel
Design-oriented model for short-channel MOS transistors based on inversion charge. LASCAS (2023)
Dayana A. Pino-Monroy, Patrick Scheer, Mohamed Khalil Bouchoucha, Carlos Galup-Montoro, Manuel J. Barragan, Philippe Cathelin, Jean-Michel Fournier, Andreia Cathelin, Sylvain Bourdel
Corrections to "Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge". IEEE Access 11 (2023)
Dayana A. Pino-Monroy, Patrick Scheer, Mohamed Khalil Bouchoucha, Carlos Galup-Montoro, Manuel J. Barragan, Philippe Cathelin, Jean-Michel Fournier, Andreia Cathelin, Sylvain Bourdel
Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge. IEEE Access 10 (2022)
Gildas Léger, Antonio J. Ginés, Valentin Gutierrez, Manuel J. Barragan
A methodology for defect detection in analog circuits based on causal feature selection. ICECS 2022 (2022)
Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragan
On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators. ATS (2022)
William R. Eisenstadt, Mark Roos, Devin Morris, José Luis González-Jiménez, Christopery Mounet, Manuel J. Barragan, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Salvador Mir, Sylvain Bourdel, Marc Margalef-Rovira, Issa Alaji, Haitham Ghanem, Guillaume Ducournau, Christophe Gaquière
Special Session on RF/5G Test. ETS (2022)
Ali Al Shakoush, Sana Ibrahim, Serge Subias, Florence Podevin, Manuel J. Barragan, Dayana A. Pino-Monroy, Imadeddine Bendjeddou, Estelle Lauga-Larroze, Laurent Fesquet, Thierry Taris, Sylvain Bourdel
Harmonic for Low Power Multi-standard Receivers. NEWCAS (2022)
Manasa Madhvaraj, Salvador Mir, Manuel J. Barragan
A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology. VLSI-SoC (2022)
Jean-Pierre David, Manuel J. Barragan
Guest Editorial Special Issue on the IEEE International NEWCAS Conference 2020. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (8) (2021)
Ankush Mamgain, Manuel J. Barragan, Salvador Mir
Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation. ETS (2021)
Sylvain Bourdel, Serge Subias, M. K. Bouchoucha, Manuel J. Barragan, A. Cathelin, Carlos Galup-Montoro
A gm/ID Design Methodology for 28 nm FD-SOI CMOS Resistive Feedback LNAs. ICECS (2021)
Marc Margalef-Rovira, Christophe Gaquière, Antonio Augusto Lisboa de Souza, Loic Vincent, Manuel J. Barragan, Emmanuel Pistono, Florence Podevin, Philippe Ferrari
mm-Wave Single-Pole Double-Throw switches: HBT- vs MOSFET-based designs. NEWCAS (2021)
Mohamad El-Chaar, Antonio Augusto Lisboa de Souza, Manuel J. Barragan, Florence Podevin, Sylvain Bourdel, Jean-Daniel Arnould
Integrated Wideband Millimeter-Wave Bias-Tee - Application to Distributed Amplifier Biasing. NEWCAS (2021)
Marc Margalef-Rovira, Olivier Occello, Abdelhalim A. Saadi, Vanessa Avramovic, Sylvie Lépilliet, Loic Vincent, Manuel J. Barragan, Emmanuel Pistono, Sylvain Bourdel, Christophe Gaquière, Philippe Ferrari
mm-Wave Through-Load Element for On-Wafer Measurement Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (8) (2021)
Renato S. Feitoza, Manuel J. Barragan, Antonio J. Ginés, Salvador Mir
-based switching SAR ADCs using a reduced-code measurement technique. NEWCAS (2020)
Renato S. Feitoza, Manuel J. Barragan, Antonio J. Ginés, Salvador Mir
-based switching SAR ADCs using an incremental analog-to-digital converter. ETS (2020)
Ekta Sharma, Abdelhalim A. Saadi, Marc Margalef-Rovira, Emmanuel Pistono, Manuel J. Barragan, Antonio Augusto Lisboa de Souza, Philippe Ferrari, Sylvain Bourdel
Design of a 77-GHz LC-VCO With a Slow-Wave Coplanar Stripline-Based Inductor. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2020)
Marc Margalef-Rovira, Abdelhalim A. Saadi, Sylvain Bourdel, Manuel J. Barragan, Emmanuel Pistono, C. Gaquiere, Philippe Ferrari
mm-Wave Through-Load Switch for in-situ Vector Network Analyzer on a 55-nm BiCMOS Technology. NEWCAS (2020)
Guillaume Renaud, Mamadou Diallo, Manuel J. Barragan, Salvador Mir
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Renato S. Feitoza, Manuel J. Barragan, Salvador Mir
Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs. VLSI-SoC (2019)
Manuel J. Barragan, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Sylvain Bourdel, Salvador Mir
On the use of causal feature selection in the context of machine-learning indirect test. DATE (2019)
Hani Malloug, Manuel J. Barragan, Salvador Mir
A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology. ETS (2019)
Florent Cilici, Gildas Léger, Manuel J. Barragan, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel
Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits. SMACD (2019)
Florent Cilici, Manuel J. Barragan, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel, Gildas Léger
Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration. ISCAS (2019)
Manuel J. Barragan, Gildas Léger
Feature selection and feature design for machine learning indirect test: a tutorial review. SMACD (2019)
Hani Malloug, Manuel J. Barragan, Salvador Mir
Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications. J. Electron. Test. 34 (3) (2018)
Marc Margalef-Rovira, Manuel J. Barragan, Ekta Sharma, Philippe Ferrari, Emmanuel Pistono, Sylvain Bourdel
An oscillation-based test technique for on-chip testing of mm-wave phase shifters. VTS (2018)
Renato S. Feitoza, Manuel J. Barragan, Salvador Mir, Daniel Dzahini
Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter. IOLTS (2018)
Ke Huang, Manuel J. Barragan
Guest Editorial: Special Issue on Analog, Mixed-Signal, and RF Testing. J. Electron. Test. 34 (3) (2018)
Florent Cilici, Manuel J. Barragan, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel
Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits. ETS (2018)
Gildas Léger, Manuel J. Barragan
Mixed-signal test automation: Are we there yet? ISCAS (2018)
Guillaume Renaud, Marc Margalef-Rovira, Manuel J. Barragan, Salvador Mir
Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs. VTS (2017)
Manuel J. Barragan, William R. Eisenstadt
Guest Editorial: Analog, Mixed-Signal and RF Testing. J. Electron. Test. 33 (3) (2017)
Manuel J. Barragan, Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
On the limits of machine learning-based test: A calibrated mixed-signal system case study. DATE (2017)
Michele Portolan, Manuel J. Barragan, Rshdee Alhakim, Salvador Mir
Mixed-signal BIST computation offloading using IEEE 1687. ETS (2017)
Gildas Léger, Manuel J. Barragan
Questioning the reliability of Monte Carlo simulation for machine learning test validation. ETS (2016)
Manuel J. Barragan, Rshdee Alhakim, Haralampos-G. D. Stratigopoulos, Matthieu Dubois, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2016)
Manuel J. Barragan, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques. IEEE Des. Test 33 (6) (2016)
Guillaume Renaud, Manuel J. Barragan, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. J. Electron. Test. 32 (4) (2016)
Antonio J. Ginés, Eduardo J. Peralías, Gildas Léger, Adoración Rueda, Guillaume Renaud, Manuel J. Barragan, Salvador Mir
Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. ETS (2016)
Gildas Léger, Manuel J. Barragan
Brownian distance correlation-directed search: A fast feature selection technique for alternate test. Integr. 55 (2016)
Manuel J. Barragan, Gildas Léger, Florence Azaïs, Ronald D. Blanton, Adit D. Singh, Stephen Sunter
Special session: Hot topics: Statistical test methods. VTS (2015)
Manuel J. Barragan, Gildas Léger
Feature selection for alternate test using wrappers: application to an RF LNA case study. DATE (2015)
Haralampos-G. D. Stratigopoulos, Manuel J. Barragan, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. ITC (2015)
Guillaume Renaud, Manuel J. Barragan, Salvador Mir, Marc Sabut
On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test. ATS (2014)
Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragan
Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs. VLSI-SoC (2014)
Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragan
Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST. VLSI-SoC (Selected Papers) (2014)
Manuel J. Barragan, Gildas Léger, Diego Vázquez, Adoración Rueda
Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation technique. LASCAS (2013)