A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs.
Guillaume RenaudManuel J. BarraganAsma LarabaHaralampos-G. D. StratigopoulosSalvador MirHervé Le GallHervé NaudetPublished in: J. Electron. Test. (2016)
Keyphrases
- circuit design
- cmos technology
- built in self test
- efficient implementation
- implementation issues
- design methodology
- design considerations
- hardware software co design
- parallel distributed
- low cost
- low power
- current status
- design process
- logical design
- case study
- infrared
- analog to digital converter
- hardware description language
- hardware architecture
- single chip
- architectural design
- experimental design