Hervé Naudet

Publication Activity (10 Years)

Years Active: 2012-2016
Publications (10 Years): 1

Top Topics

Code Generation

Processing Pipeline

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

J. Electron. Test.

Publications

Guillaume Renaud, Manuel J. Barragan, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. J. Electron. Test. 32 (4) (2016)
Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet
Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2015)
Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret
Reduced code linearity testing of pipeline adcs in the presence of noise. VTS (2013)
Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret
Reduced-Code Linearity Testing of Pipeline ADCs. IEEE Des. Test 30 (6) (2013)
Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Christophe Forel
Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs. ETS (2012)