Hervé Le Gall

Publication Activity (10 Years)

Years Active: 2015-2017
Publications (10 Years): 6

Top Topics

Cmos Technology

Navier Stokes Equations

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

J. Electron. Test.

Publications

Hani Malloug, Manuel J. Barragan Asian, Salvador Mir, Laurent Basteres, Hervé Le Gall
Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology. ETS (2017)
Manuel J. Barragan, Rshdee Alhakim, Haralampos-G. D. Stratigopoulos, Matthieu Dubois, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2016)
Manuel J. Barragan, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques. IEEE Des. Test 33 (6) (2016)
Guillaume Renaud, Manuel J. Barragan, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. J. Electron. Test. 32 (4) (2016)
Haralampos-G. D. Stratigopoulos, Manuel J. Barragan, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. ITC (2015)
Hervé Le Gall, Rshdee Alhakim, Miroslav Valka, Salvador Mir, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu
High frequency jitter estimator for SoCs. ETS (2015)