Jean-Pierre David

Publication Activity (10 Years)

Years Active: 1994-2024
Publications (10 Years): 40

Top Topics

Hybrid Architecture

Monte Carlo Tree Search

Top Venues

Publications

Tzu-Yi Chiu, Jerome Le Ny, Jean-Pierre David
Temporal Logic Explanations for Dynamic Decision Systems Using Anchors and Monte Carlo Tree Search (Abstract Reprint). AAAI (2024)
Mostafa Elbediwy, Bill Pontikakis, Alireza Ghaffari, Jean-Pierre David, Yvon Savaria
DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In-First-Out Queue. IEEE Trans. Netw. Serv. Manag. 21 (1) (2024)
MohammadHossein AskariHemmat, Ahmadreza Jeddi, Reyhane Askari Hemmat, Ivan Lazarevich, Alexander Hoffman, Sudhakar Sah, Ehsan Saboori, Yvon Savaria, Jean-Pierre David
QGen: On the Ability to Generalize in Quantization Aware Training. CoRR (2024)
Mohammadhossein Askarihemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David
BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU. CoRR (2023)
Mostafa Elbediwy, Bill Pontikakis, Jean-Pierre David, Yvon Savaria
A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. IEEE Access 11 (2023)
Dufour Jules, Yvon Savaria, Jean-Pierre David
Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries. NEWCAS (2023)
Mohammadhossein Askarihemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David
BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU. ASP-DAC (2023)
MohammadHossein AskariHemmat, Theo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. CoRR (2023)
Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, Nizar El Zarif, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria
Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference. NEWCAS (2023)
MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. ISCAS (2023)
Theo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, Nizar El Zarif, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria
Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference. CoRR (2023)
Amirali Ebrahimi, Vineeth Narayan Pullu, J. M. Pierre Langlois, Jean-Pierre David
Iterative pruning algorithm for efficient look-up table implementation of binary neural networks. NEWCAS (2023)
Tzu-Yi Chiu, Jerome Le Ny, Jean-Pierre David
Temporal logic explanations for dynamic decision systems using anchors and Monte Carlo Tree Search. Artif. Intell. 318 (2023)
Kamran Chitsaz, Gonçalo Mordido, Jean-Pierre David, François Leduc-Primeau
Training DNNs Resilient to Adversarial and Random Bit-Flips by Learning Quantization Ranges. Trans. Mach. Learn. Res. 2023 (2023)
Mengyue Su, Jean-Pierre David, Yvon Savaria, Bill Pontikakis, Thomas Luinaud
An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices. ISCAS (2022)
Jörg Ehmer, Bertrand Granado, Julien Denoulet, Yvon Savaria, Jean-Pierre David
Low Complexity Shallow Neural Network With Improved False Negative Rate for Cyber Intrusion Detection Systems. NEWCAS (2022)
Moussa Traore, J. M. Pierre Langlois, Jean-Pierre David
ASIP Accelerator for LUT-based Neural Networks Inference. NEWCAS (2022)
MohammadHossein AskariHemmat, Reyhane Askari Hemmat, Alexander Hoffman, Ivan Lazarevich, Ehsan Saboori, Olivier Mastropietro, Yvon Savaria, Jean-Pierre David
QReg: On Regularization Effects of Quantization. CoRR (2022)
Jean-Pierre David, Manuel J. Barragan
Guest Editorial Special Issue on the IEEE International NEWCAS Conference 2020. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (8) (2021)
MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David
RISC-V Barrel Processor for Deep Neural Network Acceleration. ISCAS (2021)
MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David
RISC-V Barrel Processor for Accelerator Control. FCCM (2020)
Sivakumar Chidambaram, J. M. Pierre Langlois, Jean-Pierre David
PoET-BiN: Power Efficient Tiny Binary Neurons. CoRR (2020)
Ahmed M. Abdelsalam, Ahmed Elsheikh, Sivakumar Chidambaram, Jean-Pierre David, J. M. Pierre Langlois
POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees. J. Signal Process. Syst. 92 (1) (2020)
Sivakumar Chidambaram, Pierre Langlois, Jean-Pierre David
PoET-BiN: Power Efficient Tiny Binary Neurons. MLSys (2020)
Aref Trigui, Mohamed Ali, Sami Hached, Jean-Pierre David, Ahmed Chiheb Ammari, Yvon Savaria, Mohamad Sawan
Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique. IEEE Trans. Circuits Syst. (11) (2020)
Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David
Bit-Slicing FPGA Accelerator for Quantized Neural Networks. ISCAS (2019)
Federico Montano, Tarek Ould Bachir, Jean Mahseredjian, Jean-Pierre David
A Low-Latency Reconfigurable Multistage Interconnection Network. CCECE (2019)
MohammadHossein AskariHemmat, Sina Honari, Lucas Rouhier, Christian S. Perone, Julien Cohen-Adad, Yvon Savaria, Jean-Pierre David
U-Net Fixed-Point Quantization for Medical Image Segmentation. LABELS/HAL-MICCAI/CuRIOUS@MICCAI (2019)
Alexandre Riviello, Jean-Pierre David
Binary Speech Features for Keyword Spotting Tasks. INTERSPEECH (2019)
MohammadHossein AskariHemmat, Sina Honari, Lucas Rouhier, Christian S. Perone, Julien Cohen-Adad, Yvon Savaria, Jean-Pierre David
U-Net Fixed-Point Quantization for Medical Image Segmentation. CoRR (2019)
Ahmed M. Abdelsalam, Ahmed Elsheikh, Jean-Pierre David, J. M. Pierre Langlois
POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests. DASIP (2019)
Ahmed M. Abdelsalam, Ahmed Elsheikh, Jean-Pierre David, J. M. Pierre Langlois
POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA. DASIP (2018)
Michel Gemieux, Meng Li, Yvon Savaria, Jean-Pierre David, Guchuan Zhu
A Hybrid Architecture With Low Latency Interfaces Enabling Dynamic Cache Management. IEEE Access 6 (2018)
Roberto Sanchez Correa, Jean-Pierre David
Ultra-low latency communication channels for FPGA-based HPC cluster. Integr. 63 (2018)
Federico Montano, Tarek Ould Bachir, Jean-Pierre David
An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters. IEEE Trans. Ind. Electron. 65 (1) (2018)
Sivakumar Chidambaram, Alexandre Riviello, J. M. Pierre Langlois, Jean-Pierre David
Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors. DASIP (2018)
Marc-André Daigneault, Jean-Pierre David
Automated Synthesis of Streaming Transfer Level Hardware Designs. ACM Trans. Reconfigurable Technol. Syst. 11 (2) (2018)
Himan Khanzadi, Yvon Savaria, Jean-Pierre David
A data driven CGRA Overlay Architecture with embedded processors. NEWCAS (2017)
Michel Gemieux, Yvon Savaria, Jean-Pierre David, Guchuan Zhu
A Cache-Coherent Heterogeneous Architecture for Low Latency Real Time Applications. ISORC (2017)
Jean-Pierre David
Low latency and division free Gauss-Jordan solver in floating point arithmetic. J. Parallel Distributed Comput. 106 (2017)
Matthieu Courbariaux, Yoshua Bengio, Jean-Pierre David
BinaryConnect: Training Deep Neural Networks with binary weights during propagations. NIPS (2015)
Marc-André Daigneault, Jean-Pierre David
Intermediate-Level Synthesis of a Gauss-Jordan Elimination Linear Solver. IPDPS Workshops (2015)
Jean-Pierre David
Low latency solver for linear equation systems in floating point arithmetic. ReConFig (2015)
Himan Khanzadi, Yvon Savaria, Jean-Pierre David
Mapping applications on two-level configurable hardware. AHS (2015)
Matthieu Courbariaux, Yoshua Bengio, Jean-Pierre David
BinaryConnect: Training Deep Neural Networks with binary weights during propagations. CoRR (2015)
Matthieu Courbariaux, Yoshua Bengio, Jean-Pierre David
Low precision arithmetic for deep learning. ICLR (Workshop) (2015)
Marc-André Daigneault, Jean-Pierre David
Fast description and synthesis of control-dominant circuits. Comput. Electr. Eng. 40 (4) (2014)
Jean-Pierre David
Max-hashing fragments for large data sets detection. ReConFig (2013)
Marc-André Daigneault, Jean-Pierre David
Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only). FPGA (2013)
Marc-André Daigneault, Jean-Pierre David
High-Level Description and Synthesis of Floating-Point Accumulators on FPGA. FCCM (2013)
Tarek Ould Bachir, Jean-Pierre David
Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators. ACM Trans. Reconfigurable Technol. Syst. 6 (1) (2013)
Tarek Ould Bachir, Christian Dufour, Jean Bélanger, Jean Mahseredjian, Jean-Pierre David
A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits. Math. Comput. Simul. 91 (2013)
Mathieu Allard, Patrick Grogan, Yvon Savaria, Jean-Pierre David
Two-level configuration for FPGA: A new design methodology based on a computing fabric. ISCAS (2012)
Tarek Ould Bachir, Christian Dufour, Jean Bélanger, Jean Mahseredjian, Jean-Pierre David
Effective floating-point calculation engines intended for the FPGA-based HIL simulation. ISIE (2012)
Marc-André Daigneault, Jean-Pierre David
Synchronized-transfer-level design methodology applied to hardware matrix multiplication. ReConFig (2012)
Hugo Fortin-Blanchette, Tarek Ould Bachir, Jean-Pierre David
A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters. IEEE Trans. Ind. Electron. 59 (12) (2012)
Marc-André Daigneault, Jean-Pierre David
Raising the abstraction level of HDL for control-dominant applications. FPL (2012)
Etienne Bergeron, Louis-David Perron, Marc Feeley, Jean-Pierre David
Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation. ACM Trans. Reconfigurable Technol. Syst. 4 (2) (2011)
Marc-André Daigneault, Jean-Pierre David
A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration. IEEE Trans. Instrum. Meas. 60 (6) (2011)
Marc-André Daigneault, Jean-Pierre David
Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only). FPGA (2010)
Tarek Ould Bachir, Jean-Pierre David
Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision. FCCM (2010)
Mathieu Allard, Patrick Grogan, Jean-Pierre David
A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA. ReConFig (2009)
Jean-Michel Adam, Anne Lejeune, Sandra Michelet, Jean-Pierre David, Christian Martel
Setting up On-Line Learning Experiments: The LearningLab Platform. ICALT (2008)
Marc-André Daigneault, J. M. Pierre Langlois, Jean-Pierre David
Application Specific Instruction set processor specialized for block motion estimation. ICCD (2008)
Etienne Bergeron, Marc Feeley, Jean-Pierre David
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs. CC (2008)
Jean-Pierre David, Kassem Kalach, Nicolas Tittley
Hardware Complexity of Modular Multiplication and Exponentiation. IEEE Trans. Computers 56 (10) (2007)
Jean-Pierre David, Anne Lejeune, Emmanuelle Villiot-Leclercq
Expressing Workshop Scenario with Computer Independent Model. ICALT (2006)
Christian Martel, Laurence Vignollet, Christine Ferraris, Jean-Pierre David, Anne Lejeune
LDL: An Alternative EML. ICALT (2006)
Christian Martel, Laurence Vignollet, Christine Ferraris, Jean-Pierre David, Anne Lejeune
Modeling Collaborative Learning Activities on e-Learning Platforms. ICALT (2006)
Emmanuelle Villiot-Leclercq, Jean-Pierre David, Anne Lejeune
Expressing Learning Scenarios with Computer Independent Models. ICALT (2006)
Laurence Vignollet, Jean-Pierre David, Christine Ferraris, Christian Martel, Anne Lejeune
Comparing Educational Modeling Languages on a Case Study. ICALT (2006)
Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley, Jean-Pierre David
High Level Synthesis for Data-Driven Applications. IEEE International Workshop on Rapid System Prototyping (2005)
Jean-Pierre David, Etienne Bergeron
An Intermediate Level HDL for System Level Design. FDL (2004)
Jean-Pierre David, Etienne Bergeron
A Step towards Intelligent Translation from High-Level Design to RTL. IWSOC (2004)
François Koeune, Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Pierre David, Jean-Didier Legat
An FPGA Implementation of the Linear Cryptanalysis. FPL (2002)
Jean-Jacques Quisquater, François-Xavier Standaert, Gaël Rouvroy, Jean-Pierre David, Jean-Didier Legat
A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation. FPL (2002)
Jean-Pierre David, Tony Postiau, Paul Fisette, Jean-Didier Legat
Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications. IPDPS (2001)
Jean-Pierre David, Jean-Didier Legat
A Data-Flow Oriented Co-Design for Reconfigurable Systems. International Workshop on Rapid System Prototyping (1998)
Jean-Pierre David, André Cogne, Annick Dutel
Hypermedia Exercises Prototyping and Modelising. CALISCE (1996)
Viviane Guéraud, Jean-Michel Cagnat, Jean-Pierre David, Jean-Philippe Pernin
Software environments for computer aided education. ACM SIGCSE Bull. 26 (2) (1994)