Matheus A. Cavalcante

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 45

Top Topics

Matrix Multiplication

Optical Networks

Highly Efficient

Top Venues

IEEE Trans. Computers

Publications

Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. CoRR (2024)
Matteo Perotti, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli, Luca Benini
Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor. IEEE Trans. Computers 73 (7) (2024)
Nesara Eranna Bethur, Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (7) (2024)
Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. CoRR (2024)
Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. CoRR (2024)
Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. ACM Great Lakes Symposium on VLSI (2024)
Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. DATE (2024)
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. CoRR (2024)
Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. CoRR (2023)
Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini
MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory. IEEE Trans. Computers 72 (12) (2023)
Samuel Riedel, Matheus A. Cavalcante, Manos Frouzakis, Domenic Wüthrich, Enis Mustafa, Arlind Billa, Luca Benini
MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS. ICECS (2023)
Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler
Sparse Hamming Graph: A Customizable Network-on-Chip Topology. DAC (2023)
MohammadHossein AskariHemmat, Theo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. CoRR (2023)
MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. ISCAS (2023)
Matteo Perotti, Matheus A. Cavalcante, Alessandro Ottaviano, Jiantao Liu, Luca Benini
Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini
MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory. CoRR (2023)
Matheus A. Cavalcante, Matteo Perotti, Samuel Riedel, Luca Benini
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. CoRR (2023)
Tim Fischer, Michael Rogenmoser, Matheus A. Cavalcante, Frank K. Gürkaynak, Luca Benini
FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic. CoRR (2023)
Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement. DAC (2023)
Tim Fischer, Michael Rogenmoser, Matheus A. Cavalcante, Frank K. Gürkaynak, Luca Benini
FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic. IEEE Des. Test 40 (6) (2023)
Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. DAC (2023)
Samuel Riedel, Gua Hao Khov, Sergio Mazzola, Matheus A. Cavalcante, Renzo Andri, Luca Benini
MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster. DATE (2023)
Matteo Perotti, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli, Luca Benini
Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV1.0 Compliant Open-Source Processor. CoRR (2023)
Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. ASAP (2022)
Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. ICCAD (2022)
Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement. CoRR (2022)
Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. CoRR (2022)
Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. DATE (2022)
Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim
Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. ISLPED (2022)
Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. ISVLSI (2022)
Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler
Sparse Hamming Graph: A Customizable Network-on-Chip Topology. CoRR (2022)
Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. IEEE Trans. Computers 71 (8) (2022)
Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. CoRR (2022)
Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. CoRR (2022)
Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. DATE (2021)
Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. CoRR (2021)
Matheus A. Cavalcante, Andreas Kurth, Fabian Schuiki, Luca Benini
Design of an open-source bridge between non-coherent burst-based and coherent cache-line-based memory systems. CF (2020)
Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. CoRR (2020)
Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. CoRR (2020)
Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. IEEE Trans. Very Large Scale Integr. Syst. 28 (2) (2020)
Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini
Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI. CoRR (2019)
Matheus A. Cavalcante, Helder A. Pereira, Daniel A. R. Chaves, Raul C. Almeida Jr.
Evolutionary Multiobjective Strategy for Regenerator Placement in Elastic Optical Networks. IEEE Trans. Commun. 66 (8) (2018)
Matheus A. Cavalcante, Helder A. Pereira, Daniel A. R. Chaves, Raul C. Almeida Jr.
Optimizing the cost function of power series routing algorithm for transparent elastic optical networks. Opt. Switch. Netw. 29 (2018)
Matheus A. Cavalcante, Helder A. Pereira, Raul C. Almeida Jr.
SimEON: an open-source elastic optical network simulator for academic and industrial purposes. Photonic Netw. Commun. 34 (2) (2017)
Daniel A. R. Chaves, Matheus A. Cavalcante, Helder A. Pereira, Raul C. Almeida
A case study of regenerator placement and regenerator assignment in dynamic translucent elastic optical networks. ICTON (2016)