Nils Wistoff

Publication Activity (10 Years)

Years Active: 2020-2024
Publications (10 Years): 17

Top Topics

Instruction Set Architecture

Temporal Ordering

Error Tolerance

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Luca Valente, Alessandro Nadalini, Asif Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto, Daniele Palossi, Luca Benini, Davide Rossi
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation. CoRR (2024)
Riccardo Tedeschi, Luca Valente, Gianmarco Ottavi, Enrico Zelioli, Nils Wistoff, Massimiliano Giacometti, Abdul Basit Sajjad, Luca Benini, Davide Rossi
Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor. CoRR (2024)
Luca Valente, Alessandro Nadalini, Asif Hussain Chiralil Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto, Daniele Palossi, Luca Benini, Davide Rossi
A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (5) (2024)
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. CoRR (2024)
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Gernot Heiser, Luca Benini
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning. IEEE Trans. Computers 72 (5) (2023)
Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino
Towards a RISC-V Open Platform for Next-generation Automotive ECUs. MECO (2023)
Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino
Towards a RISC-V Open Platform for Next-generation Automotive ECUs. CoRR (2023)
Marcelo Orenes-Vera, Hyunsung Yun, Nils Wistoff, Gernot Heiser, Luca Benini, David Wentzlaff, Margaret Martonosi
AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware. MICRO (2023)
Luca Valente, A. Veeran, Mattia Sinigaglia, Yvan Tortorella, Alessandro Nadalini, Nils Wistoff, Bruno Sá, Angelo Garofalo, Rafail Psiakis, M. Tolba, Ari Kulmala, Nimisha Limaye, Ozgur Sinanoglu, Sandro Pinto, Daniele Palossi, Luca Benini, Baker Mohammad, Davide Rossi
Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. HCS (2023)
Scott Buckley, Robert Sison, Nils Wistoff, Curtis Millar, Toby Murray, Gerwin Klein, Gernot Heiser
Proving the Absence of Microarchitectural Timing Channels. CoRR (2023)
Michael Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank K. Gürkaynak, Luca Benini
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster. CoRR (2022)
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Gernot Heiser, Luca Benini
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning. CoRR (2022)
Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. ASAP (2022)
Michael Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank K. Gürkaynak, Luca Benini
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster. ISVLSI (2022)
Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. CoRR (2022)
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core. DATE (2021)
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser
Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core. CoRR (2020)