David Wentzlaff

ORCID

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 62

Top Venues

Massachusetts Institute of Technology, Cambridge, MA, USA (PHD)

Education History

Massachusetts Institute of Technology, Cambridge, MA, USA

PHD

Publications

Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff
MuchiSim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems. ISPASS (2024)
Kaifeng Xu, Georgios Tziantzioulis, David Wentzlaff
MindPalace: A Framework for Studying Microarchitecture Design of Function-as-a-Service. ISPASS (2024)
Hengrui Zhang, August Ning, Rohan Baskar Prabhakar, David Wentzlaff
LLMCompass: Enabling Efficient Hardware Design for Large Language Model Inference. ISCA (2024)
Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff
Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems. CoRR (2023)
Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi
Massive Data-Centric Parallelism in the Chiplet Era. CoRR (2023)
Hengrui Zhang, August Ning, Rohan Prabhakar, David Wentzlaff
A Hardware Evaluation Framework for Large Language Model Inference. CoRR (2023)
Grigory Chirkov, David Wentzlaff
Seizing the Bandwidth Scaling of On-Package Interconnect in a Post-Moore's Law World. ICS (2023)
Marcelo Orenes-Vera, Margaret Martonosi, David Wentzlaff
Using LLMs to Facilitate Formal Verification of RTL. CoRR (2023)
Grigory Chirkov, David Wentzlaff
SMAPPIC: Scalable Multi-FPGA Architecture Prototype Platform in the Cloud. ASPLOS (2) (2023)
Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff
DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications. CoRR (2023)
Ting-Jung Chang, Ang Li, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul J. Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff
1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA. CICC (2023)
Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi
Tascade: Hardware Support for Atomic-free, Asynchronous and Efficient Reduction Trees. CoRR (2023)
Yuchen Liu, Georgios Tziantzioulis, David Wentzlaff
Building Efficient Neural Prefetcher. MEMSYS (2023)
Fei Gao, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul J. Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca P. Carloni, David Wentzlaff
, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET. CICC (2023)
Marcelo Orenes-Vera, Hyunsung Yun, Nils Wistoff, Gernot Heiser, Luca Benini, David Wentzlaff, Margaret Martonosi
AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware. MICRO (2023)
Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi
Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications. HPCA (2023)
Ang Li, August Ning, David Wentzlaff
Duet: Creating Harmony between Processors and Embedded FPGAs. HPCA (2023)
Ang Li, August Ning, David Wentzlaff
Duet: Creating Harmony between Processors and Embedded FPGAs. CoRR (2023)
August Ning, Georgios Tziantzioulis, David Wentzlaff
Supply Chain Aware Computer Architecture. ISCA (2023)
Georgios Tziantzioulis, Ting-Jung Chang, Jonathan Balkind, Jinzheng Tu, Fei Gao, David Wentzlaff
OPDB: A Scalable and Modular Design Benchmark. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (6) (2022)
Fei Gao, Georgios Tziantzioulis, David Wentzlaff
FracDRAM: Fractional Values in Off-the-Shelf DRAM. MICRO (2022)
Yuchen Liu, David Wentzlaff, Sun-Yuan Kung
Class-Discriminative CNN Compression. ICPR (2022)
Yuchen Liu, Sun-Yuan Kung, David Wentzlaff
Evolving transferable neural pruning functions. GECCO (2022)
Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi
Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications. CoRR (2022)
Marcelo Orenes-Vera, Aninda Manocha, Jonathan Balkind, Fei Gao, Juan L. Aragón, David Wentzlaff, Margaret Martonosi
Tiny but mighty: designing and realizing scalable latency tolerance for manycore SoCs. ISCA (2022)
Yuchen Liu, David Wentzlaff, Sun-Yuan Kung
Class-Discriminative CNN Compression. CoRR (2021)
Ang Li, David Wentzlaff
PRGA: An Open-Source FPGA Research and Prototyping Framework. FPGA (2021)
Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff, Margaret Martonosi
AutoSVA: Democratizing Formal Verification of RTL Module Interactions. DAC (2021)
Yuchen Liu, S. Y. Kung, David Wentzlaff
Evolving Transferable Pruning Functions. CoRR (2021)
Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff, Margaret Martonosi
AutoSVA: Democratizing Formal Verification of RTL Module Interactions. CoRR (2021)
Ting-Jung Chang, Zhuozhi Yao, Barry P. Rand, David Wentzlaff
Organic-Flow: An Open-Source Organic Standard Cell Library and Process Development Kit. DATE (2020)
Jonathan Balkind, Katie Lim, Michael Schaffner, Fei Gao, Grigory Chirkov, Ang Li, Alexey Lavrov, Tri M. Nguyen, Yaosheng Fu, Florian Zaruba, Kunal Gulati, Luca Benini, David Wentzlaff
BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research. ASPLOS (2020)
Yuchen Liu, David Wentzlaff, Sun-Yuan Kung
Rethinking Class-Discrimination Based CNN Channel Pruning. CoRR (2020)
Ang Li, David Wentzlaff
Cycle-Free FPGA Routing Graphs. FPGA (2020)
Ang Li, Ting-Jung Chang, David Wentzlaff
Automated Design of FPGAs Facilitated by Cycle-Free Routing. FPL (2020)
Jonathan Balkind, Ting-Jung Chang, Paul J. Jackson, Georgios Tziantzioulis, Ang Li, Fei Gao, Alexey Lavrov, Grigory Chirkov, Jinzheng Tu, Mohammad Shahrad, David Wentzlaff
OpenPiton at 5: A Nexus for Open and Agile Hardware Design. IEEE Micro 40 (4) (2020)
Alexey Lavrov, David Wentzlaff
HyperTRIO: Hyper-Tenant Translation of I/O Addresses. ISCA (2020)
Yuxuan Jiang, Mohammad Shahrad, David Wentzlaff, Danny H. K. Tsang, Carlee Joe-Wong
Burstable Instances for Clouds: Performance Modeling, Equilibrium Analysis, and Revenue Maximization. IEEE/ACM Trans. Netw. 28 (6) (2020)
Mina Tahmasbi Arashloo, Alexey Lavrov, Manya Ghobadi, Jennifer Rexford, David Walker, David Wentzlaff
Enabling Programmable Transport Protocols in High-Speed NICs. NSDI (2020)
Katie Lim, Jonathan Balkind, David Wentzlaff
JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores. FPGA (2019)
Fei Gao, Georgios Tziantzioulis, David Wentzlaff
ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs. MICRO (2019)
Yuxuan Jiang, Mohammad Shahrad, David Wentzlaff, Danny H. K. Tsang, Carlee Joe-Wong
Burstable Instances for Clouds: Performance Modeling, Equilibrium Analysis, and Revenue Maximization. INFOCOM (2019)
Adi Fuchs, David Wentzlaff
The Accelerator Wall: Limits of Chip Specialization. HPCA (2019)
Jonathan Balkind, Michael McKeown, Yaosheng Fu, Tri Minh Nguyen, Yanqi Zhou, Alexey Lavrov, Mohammad Shahrad, Adi Fuchs, Samuel Payne, Xiaohua Liang, Matthew Matl, David Wentzlaff
OpenPiton: an open source hardware platform for your research. Commun. ACM 62 (12) (2019)
Mohammad Shahrad, Jonathan Balkind, David Wentzlaff
Architectural Implications of Function-as-a-Service Computing. MICRO (2019)
Tri Minh Nguyen, Adi Fuchs, David Wentzlaff
CABLE: A CAche-Based Link Encoder for Bandwidth-Starved Manycores. MICRO (2018)
Tri Minh Nguyen, David Wentzlaff
PiCL: A Software-Transparent, Persistent Cache Log for Nonvolatile Main Memory. MICRO (2018)
Adi Fuchs, David Wentzlaff
Scaling Datacenter Accelerators with Compute-Reuse Architectures. ISCA (2018)
Mohammad Shahrad, Arsalan Mosenia, Liwei Song, Mung Chiang, David Wentzlaff, Prateek Mittal
Acoustic Denial of Service Attacks on Hard Disk Drives. ASHES@CCS (2018)
Michael McKeown, Alexey Lavrov, Mohammad Shahrad, Paul J. Jackson, Yaosheng Fu, Jonathan Balkind, Tri Minh Nguyen, Katie Lim, Yanqi Zhou, David Wentzlaff
Power and Energy Characterization of an Open Source 25-Core Manycore Processor. HPCA (2018)
Katie Lim, Jonathan Balkind, David Wentzlaff
JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores. CoRR (2018)
Yanqi Zhou, Sameer Wagh, Prateek Mittal, David Wentzlaff
Camouflage: Memory Traffic Shaping to Mitigate Timing Attacks. HPCA (2017)
Ting-Jung Chang, Zhuozhi Yao, Paul J. Jackson, Barry P. Rand, David Wentzlaff
Architectural tradeoffs for biodegradable computing. MICRO (2017)
Mohammad Shahrad, David Wentzlaff
Towards Deploying Decommissioned Mobile Devices as Cheap Energy-Efficient Compute Nodes. HotCloud (2017)
Mohammad Shahrad, Cristian Klein, Liang Zheng, Mung Chiang, Erik Elmroth, David Wentzlaff
Incentivizing self-capping to increase cloud utilization. SoCC (2017)
Michael McKeown, Yaosheng Fu, Tri Minh Nguyen, Yanqi Zhou, Jonathan Balkind, Alexey Lavrov, Mohammad Shahrad, Samuel Payne, David Wentzlaff
Piton: A Manycore Processor for Multitenant Clouds. IEEE Micro 37 (2) (2017)
Mohammad Shahrad, Arsalan Mosenia, Liwei Song, Mung Chiang, David Wentzlaff, Prateek Mittal
Acoustic Denial of Service Attacks on HDDs. CoRR (2017)
Mohammad Shahrad, David Wentzlaff
Availability Knob: Flexible User-Defined Availability in the Cloud. SoCC (2016)
Michael McKeown, Yaosheng Fu, Tri Minh Nguyen, Yanqi Zhou, Jonathan Balkind, Alexey Lavrov, Mohammad Shahrad, Samuel Payne, David Wentzlaff
Piton: A 25-core academic manycore research processor. Hot Chips Symposium (2016)
Jonathan Balkind, Michael McKeown, Yaosheng Fu, Tri Minh Nguyen, Yanqi Zhou, Alexey Lavrov, Mohammad Shahrad, Adi Fuchs, Samuel Payne, Xiaohua Liang, Matthew Matl, David Wentzlaff
OpenPiton: An Open Source Manycore Research Framework. ASPLOS (2016)
Yanqi Zhou, David Wentzlaff
MITTS: Memory Inter-arrival Time Traffic Shaping. ISCA (2016)
Yanqi Zhou, Henry Hoffmann, David Wentzlaff
CASH: Supporting IaaS Customers with a Sub-core Configurable Architecture. ISCA (2016)
Yaosheng Fu, Tri Minh Nguyen, David Wentzlaff
Coherence domain restriction on large scale systems. MICRO (2015)
Tri Minh Nguyen, David Wentzlaff
MORC: a manycore-oriented compressed cache. MICRO (2015)
Michael McKeown, Jonathan Balkind, David Wentzlaff
Execution Drafting: Energy Efficiency through Computation Deduplication. MICRO (2014)
Yaosheng Fu, David Wentzlaff
PriME: A parallel and distributed simulator for thousand-core chips. ISPASS (2014)
Yanqi Zhou, David Wentzlaff
The sharing architecture: sub-core configurability for IaaS clouds. ASPLOS (2014)
Lamia Youseff, Nathan Beckmann, Harshad Kasture, Charles Gruenwald III, David Wentzlaff, Anant Agarwal
The case for elastic operating system services in fos. DAC (2012)
David Wentzlaff, Christopher J. Jackson, Patrick Griffin, Anant Agarwal
Configurable fine-grain protection for multicore processor virtualization. ISCA (2012)
David Wentzlaff, Charles Gruenwald III, Nathan Beckmann, Kevin Modzelewski, Adam Belay, Lamia Youseff, Jason E. Miller, Anant Agarwal
An operating system for multicore and clouds: mechanisms and implementation. SoCC (2010)
Henry Hoffmann, David Wentzlaff, Anant Agarwal
Remote Store Programming. HiPEAC (2010)
David Wentzlaff, Anant Agarwal
Factored operating systems (fos): the case for a scalable operating system for multicores. ACM SIGOPS Oper. Syst. Rev. 43 (2) (2009)
Shane Bell, Bruce Edwards, John Amann, Rich Conlin, Kevin Joyce, Vince Leung, John MacKay, Mike Reif, Liewei Bao, John F. Brown III, Matthew Mattina, Chyi-Chang Miao, Carl Ramey, David Wentzlaff, Walker Anderson, Ethan Berger, Nat Fairbanks, Durlov Khan, Froilan Montenegro, Jay Stickney, John Zook
TILE64 - Processor: A 64-Core SoC with Mesh Interconnect. ISSCC (2008)
David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal
On-Chip Interconnection Architecture of the Tile Processor. IEEE Micro 27 (5) (2007)
David Wentzlaff, Anant Agarwal
Constructing Virtual Architectures on a Tiled Processor. CGO (2006)
David Wentzlaff, Anant Agarwal
A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation. FCCM (2004)
Michael B. Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul R. Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew I. Frank, Saman P. Amarasinghe, Anant Agarwal
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. ISCA (2004)
Jason Sungtae Kim, Michael Bedford Taylor, Jason E. Miller, David Wentzlaff
Energy characterization of a tiled architecture processor with on-chip networks. ISLPED (2003)
Michael B. Taylor, Jason Sungtae Kim, Jason E. Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffmann, Paul R. Johnson, Jae W. Lee, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matthew I. Frank, Saman P. Amarasinghe, Anant Agarwal
The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs. IEEE Micro 22 (2) (2002)

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Publication Activity (10 Years)

Top Topics

Top Venues

David Wentzlaff