Energy characterization of a tiled architecture processor with on-chip networks.
Jason Sungtae KimMichael Bedford TaylorJason E. MillerDavid WentzlaffPublished in: ISLPED (2003)
Keyphrases
- high speed
- level parallelism
- single chip
- functional units
- multithreading
- analog vlsi
- ibm zenterprise
- parallel architecture
- instruction set
- high bandwidth
- low cost
- memory access
- multi processor
- vlsi implementation
- processor core
- memory subsystem
- chip design
- energy consumption
- industry standard
- real time
- network structure
- floating point arithmetic
- functional verification
- processing elements
- ibm power processor
- parallel processing
- cmos image sensor
- social networks
- random access memory
- future internet
- energy efficiency
- memory bandwidth
- resource manager
- memory management
- network on chip
- processing units
- floating point
- wireless networks
- embedded dram