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Paul Scheffler
ORCID
Publication Activity (10 Years)
Years Active: 2020-2024
Publications (10 Years): 15
Top Topics
Lightweight
Parallel Processing
Mechanism Design
Linear Algebra
Top Venues
CoRR
DATE
IEEE Trans. Circuits Syst. II Express Briefs
IEEE Trans. Computers
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Publications
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Thomas Benz
,
Michael Rogenmoser
,
Paul Scheffler
,
Samuel Riedel
,
Alessandro Ottaviano
,
Andreas Kurth
,
Torsten Hoefler
,
Luca Benini
A High-Performance, Energy-Efficient Modular DMA Engine Architecture.
IEEE Trans. Computers
73 (1) (2024)
Chi Zhang
,
Paul Scheffler
,
Thomas Benz
,
Matteo Perotti
,
Luca Benini
AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads.
DATE
(2023)
Paul Scheffler
,
Florian Zaruba
,
Fabian Schuiki
,
Torsten Hoefler
,
Luca Benini
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra.
CoRR
(2023)
Chi Zhang
,
Paul Scheffler
,
Thomas Benz
,
Matteo Perotti
,
Luca Benini
Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV.
CoRR
(2023)
Alessandro Ottaviano
,
Thomas Benz
,
Paul Scheffler
,
Luca Benini
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In.
IEEE Trans. Circuits Syst. II Express Briefs
70 (10) (2023)
Alessandro Ottaviano
,
Thomas Benz
,
Paul Scheffler
,
Luca Benini
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In.
CoRR
(2023)
Thomas Benz
,
Michael Rogenmoser
,
Paul Scheffler
,
Samuel Riedel
,
Alessandro Ottaviano
,
Andreas Kurth
,
Torsten Hoefler
,
Luca Benini
A High-performance, Energy-efficient Modular DMA Engine Architecture.
CoRR
(2023)
Paul Scheffler
,
Florian Zaruba
,
Fabian Schuiki
,
Torsten Hoefler
,
Luca Benini
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra.
IEEE Trans. Parallel Distributed Syst.
34 (12) (2023)
Chi Zhang
,
Paul Scheffler
,
Thomas Benz
,
Matteo Perotti
,
Luca Benini
AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads.
CoRR
(2022)
Gianna Paulin
,
Matheus A. Cavalcante
,
Paul Scheffler
,
Luca Bertaccini
,
Yichao Zhang
,
Frank K. Gürkaynak
,
Luca Benini
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters.
ISVLSI
(2022)
Gianna Paulin
,
Matheus A. Cavalcante
,
Paul Scheffler
,
Luca Bertaccini
,
Yichao Zhang
,
Frank K. Gürkaynak
,
Luca Benini
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters.
CoRR
(2022)
Paul Scheffler
,
Florian Zaruba
,
Fabian Schuiki
,
Torsten Hoefler
,
Luca Benini
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra.
DATE
(2021)
Samuel Riedel
,
Fabian Schuiki
,
Paul Scheffler
,
Florian Zaruba
,
Luca Benini
Banshee: A Fast LLVM-Based RISC-V Binary Translator.
ICCAD
(2021)
Paul Scheffler
,
Florian Zaruba
,
Fabian Schuiki
,
Torsten Hoefler
,
Luca Benini
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra.
CoRR
(2020)
Ines Schulze-Horn
,
Sabrina Hueren
,
Paul Scheffler
,
Holger Schiele
Artificial Intelligence in Purchasing: Facilitating Mechanism Design-based Negotiations.
Appl. Artif. Intell.
34 (8) (2020)