Paul Scheffler

Publication Activity (10 Years)

Years Active: 2020-2024
Publications (10 Years): 22

Top Topics

Parallel Processing

Mechanism Design

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Philippe Sauter, Thomas Benz, Paul Scheffler, Frank K. Gürkaynak, Luca Benini
Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design? CoRR (2024)
Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini
A High-Performance, Energy-Efficient Modular DMA Engine Architecture. IEEE Trans. Computers 73 (1) (2024)
Paul Scheffler, Philippe Sauter, Thomas Benz, Frank K. Gürkaynak, Luca Benini
Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS. CoRR (2024)
Philippe Sauter, Thomas Benz, Paul Scheffler, Zerun Jiang, Beat Muheim, Frank K. Gürkaynak, Luca Benini
Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC. CoRR (2024)
Simone Manoni, Paul Scheffler, Alfio Di Mauro, Luca Zanatta, Andrea Acquaviva, Luca Benini, Andrea Bartolini
NARS: Neuromorphic Acceleration through Register-Streaming Extensions on RISC-V Cores. CF (Companion) (2024)
Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini
Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV. DATE (2024)
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. CoRR (2024)
Paul Scheffler, Luca Colagrande, Luca Benini
SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers. CoRR (2024)
Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini
AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads. DATE (2023)
Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. CoRR (2023)
Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini
Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV. CoRR (2023)
Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca Benini
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca Benini
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In. CoRR (2023)
Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini
A High-performance, Energy-efficient Modular DMA Engine Architecture. CoRR (2023)
Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. IEEE Trans. Parallel Distributed Syst. 34 (12) (2023)
Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini
AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads. CoRR (2022)
Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. ISVLSI (2022)
Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. CoRR (2022)
Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. DATE (2021)
Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini
Banshee: A Fast LLVM-Based RISC-V Binary Translator. ICCAD (2021)
Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. CoRR (2020)
Ines Schulze-Horn, Sabrina Hueren, Paul Scheffler, Holger Schiele
Artificial Intelligence in Purchasing: Facilitating Mechanism Design-based Negotiations. Appl. Artif. Intell. 34 (8) (2020)