Samuel Riedel

Publication Activity (10 Years)

Years Active: 2020-2024
Publications (10 Years): 25

Top Topics

Parallel Architectures

Multi Core Architecture

Top Venues

IEEE Trans. Computers

Publications

Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation. CoRR (2024)
Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems Through Polling-Free and Retry-Free Operation. DATE (2024)
Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini
A High-Performance, Energy-Efficient Modular DMA Engine Architecture. IEEE Trans. Computers 73 (1) (2024)
Nesara Eranna Bethur, Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (7) (2024)
Sergio Mazzola, Samuel Riedel, Luca Benini
Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters. CoRR (2024)
Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. CoRR (2024)
Sudipta Das, Samuel Riedel, Marco Bertuletti, Luca Benini, Moritz Brunion, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic
3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. ISCAS (2024)
Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. ACM Great Lakes Symposium on VLSI (2024)
Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster. SAMOS (2023)
Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini
MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory. IEEE Trans. Computers 72 (12) (2023)
Samuel Riedel, Matheus A. Cavalcante, Manos Frouzakis, Domenic Wüthrich, Enis Mustafa, Arlind Billa, Luca Benini
MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS. ICECS (2023)
Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini
MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory. CoRR (2023)
Matheus A. Cavalcante, Matteo Perotti, Samuel Riedel, Luca Benini
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. CoRR (2023)
Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini
A High-performance, Energy-efficient Modular DMA Engine Architecture. CoRR (2023)
Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster. CoRR (2023)
Samuel Riedel, Gua Hao Khov, Sergio Mazzola, Matheus A. Cavalcante, Renzo Andri, Luca Benini
MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster. DATE (2023)
Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. ICCAD (2022)
Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. CoRR (2022)
Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. DATE (2022)
Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim
Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. ISLPED (2022)
Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. DATE (2021)
Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini
Banshee: A Fast LLVM-Based RISC-V Binary Translator. ICCAD (2021)
Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. CoRR (2021)
Andreas Kurth, Samuel Riedel, Florian Zaruba, Torsten Hoefler, Luca Benini
ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor. DAC (2020)
Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. CoRR (2020)