José Silva-Martínez

ORCID

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 33

Top Venues

MWSCAS

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Jian Shao, Aydin Ilker Karsilayan, Christopher T. Rodenbeck, José Silva-Martínez
An Interference-Tolerant Synchronization Scheme for Wireless Communication Systems Based on Direct Sequence Spread Spectrum. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
José Silva-Martínez, Xiaosen Liu, Dadian Zhou
Recent Advances on Linear Low-Dropout Regulators. IEEE Trans. Circuits Syst. II Express Briefs 68 (2) (2021)
Jian Shao, Aydin Ilker Karsilayan, Christopher T. Rodenbeck, José Silva-Martínez
An Efficient Sinusoid-Like Pseudo Random Sequence Modulator/Demodulator System With Reduced Adjacent Channel Leakage and High Rejection to Random and Systematic Interference. IEEE Trans. Circuits Syst. (11) (2020)
Juan A. Bozzo, Angel Abusleme, José Silva-Martínez
A Blind Calibration Scheme for Switched-Capacitor Pipeline Analog-to-Digital Converters. LASCAS (2020)
Dadian Zhou, Junning Jiang, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator. IEEE J. Solid State Circuits 55 (8) (2020)
Chulhyun Park, Tao Chen, Kyoohyun Noh, Dadian Zhou, Suraj Prakash, Mohammadhossein Naderi Alizadeh, Aydin I. Karsilayan, Degang Chen, Randall L. Geiger, José Silva-Martínez
A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier. IEEE Trans. Circuits Syst. (11) (2020)
José Silva-Martínez, José G. Delgado-Frias
MWSCAS Guest Editorial Special Issue Based on the 62nd International Midwest Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. (10) (2020)
Tao Chen, Chulhyun Park, Shravan K. Chaganti, José Silva-Martínez, Randall L. Geiger, Degang Chen
An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method. IEEE Trans. Instrum. Meas. 69 (3) (2020)
Tao Chen, Chulhyun Park, Hao Meng, Dadian Zhou, José Silva-Martínez, Randall L. Geiger, Degang Chen
A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test. IEEE Trans. Instrum. Meas. 69 (6) (2020)
Jusung Kim, Junning Jiang, José Silva-Martínez, Aydin Ilker Karsilayan
A 3 to 6 GHz Highly Linear I-Channel Receiver with over +3.0 dBm In-Band P1dB and 200 MHz Baseband Bandwidth Suitable for 5G Wireless and Cognitive Radio Applications. ISCAS (2020)
Mohammad H. Naderi, Chulhyun Park, Suraj Prakash, Martin Kinyua, Eric G. Soenen, José Silva-Martínez
A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
Junning Jiang, Jusung Kim, Aydin Ilker Karsilayan, José Silva-Martínez
and 200-MHz Baseband Bandwidth Suitable for 5G Wireless and Cognitive Radio Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2019)
Christopher T. Rodenbeck, Matthew Martinez, Joshua B. Beun, José Silva-Martínez, Aydin Ilker Karsilayan, Robert Liechty
When Less Is More ... Few Bit ADCs in RF Systems. IEEE Access 7 (2019)
Dadian Zhou, Carlos Briseno-Vidrios, Junning Jiang, Chulhyun Park, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
José Silva-Martínez, Tanwei Yan, Junning Jiang, Jian Shao
Efficient Broadband Class AB Amplifier. MWSCAS (2019)
Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. IEEE J. Solid State Circuits 53 (11) (2018)
Qiyuan Liu, Alexander Edward, Dadian Zhou, José Silva-Martínez
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26 (4) (2018)
Venkatraman Natarajan, Mohammad H. Naderi, José Silva-Martínez
Low noise RF quadrature VCO using tail-switch network-based coupling in 40 nm CMOS. CICC (2018)
John S. Mincey, Eric C. Su, José Silva-Martínez, Christopher T. Rodenbeck
A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications. IEEE Trans. Very Large Scale Integr. Syst. 26 (6) (2018)
Mohammad H. Naderi, Suraj Prakash, José Silva-Martínez
Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Aditya Bommireddipalli, Dadian Zhou, Claudio Talarico, José Silva-Martínez, Aydin I. Karsilayan
A 200MSPS time-interleaved 12-bit ADC system with digital calibration. MWSCAS (2017)
Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, José Silva-Martínez
A 13bit 200MS/S pipeline ADC with current-mode MDACs. ISCAS (2017)
Haoyu Qian, José Silva-Martínez
Multitone ACLR and Its Applications to Linear PA Design. IEEE Trans. Circuits Syst. II Express Briefs (10) (2017)
Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez
A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage. IEEE J. Solid State Circuits 52 (3) (2017)
John S. Mincey, Carlos Briseno-Vidrios, José Silva-Martínez, Christopher T. Rodenbeck
-C Filter Employing Current-Reuse Differential Difference Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs (6) (2017)
Qiyuan Liu, Alexander Edward, Martin Kinyua, Eric G. Soenen, José Silva-Martínez
A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques. IEEE J. Solid State Circuits 52 (6) (2017)
Jun Zhou, Amir Tofighi Zavareh, Robin Gupta, Liang Liu, Zhongfeng Wang, Brian M. Sadler, José Silva-Martínez, Sebastian Hoyos
Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2017)
Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Negar Rashidi, José Silva-Martínez
High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications. MWSCAS (2017)
Alexander Edward, Qiyuan Liu, Carlos Briseno-Vidrios, Martin Kinyua, Eric G. Soenen, Aydin Ilker Karsilayan, José Silva-Martínez
A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS. IEEE J. Solid State Circuits 52 (2) (2017)
Mohammad H. Naderi, José Silva-Martínez
Algorithmic-pipelined ADC with a modified residue curve for better linearity. MWSCAS (2017)
Dadian Zhou, Claudio Talarico, José Silva-Martínez
A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration. SoCC (2016)
Haoyu Qian, Qiyuan Liu, José Silva-Martínez, Sebastian Hoyos
A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS. IEEE J. Solid State Circuits 51 (3) (2016)
Carlos Briseno-Vidrios, Alexander Edward, Negar Rashidi, José Silva-Martínez
A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer. IEEE J. Solid State Circuits 51 (6) (2016)
Hyung-Joon Jeon, José Silva-Martínez, Sebastian Hoyos
A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain. IEEE Trans. Very Large Scale Integr. Syst. 23 (1) (2015)
Hemasundar Mohan Geddada, Chang-Joon Park, Hyung-Joon Jeon, José Silva-Martínez, Aydin Ilker Karsilayan, Douglas Garrity
Design Techniques to Improve Blocker Tolerance of Continuous-Time ΔΣ ADCs. IEEE Trans. Very Large Scale Integr. Syst. 23 (1) (2015)
Yung-Chung Lo, Negar Rashidi, Yin-Huan Hwang, José Silva-Martínez
A 0.6ps jitter 2-16 GHz 130nm CMOS frequency synthesizer for broadband applications. ISCAS (2015)
Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez
A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique. VLSIC (2015)
Chang-Joon Park, Marvin Onabajo, Hemasundar Mohan Geddada, Aydin Ilker Karsilayan, José Silva-Martínez
Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma-Delta Modulators. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Hemasundar Mohan Geddada, Chang-Joon Park, José Silva-Martínez, Aydin Ilker Karsilayan
Blocker tolerant wideband continuous time sigma-delta modulator for wireless applications. MWSCAS (2014)
Alexander Edward, José Silva-Martínez
General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators. IEEE Trans. Circuits Syst. II Express Briefs (7) (2014)
Saiteja Damera, Aydin Ilker Karsilayan, José Silva-Martínez
Design of minimally-invasive all-pole analog lowpass filters. MWSCAS (2014)
Josep Altet, Eduardo Aldrete-Vidrio, Ferran Reverter, Didac Gómez, José Luis González, Marvin Onabajo, José Silva-Martínez, B. Martineau, X. Perpiñà, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Xavier Aragonès, Xavier Jordà, Miquel Vellvehí, Stefan Dilhaire, Salvador Mir, Diego Mateo
Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes. MWSCAS (2014)
José Silva-Martínez, Edgar Sánchez-Sinencio, José G. Delgado-Frias, Randall L. Geiger
Welcome to MWSCAS 2014. MWSCAS (2014)
Chang-Joon Park, José Silva-Martínez, Marvin Onabajo
Design techniques for external capacitor-less LDOs with high PSR over wide frequency range. MWSCAS (2014)
Chang-Joon Park, Marvin Onabajo, José Silva-Martínez
External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4-4 MHz Range. IEEE J. Solid State Circuits 49 (2) (2014)
Haoyu Qian, José Silva-Martínez
A 44.9% PAE digitally-assisted linear power amplifier in 40 nm CMOS. A-SSCC (2014)
Hyung-Joon Jeon, Raghavendra Kulkarni, Yung-Chung Lo, Jusung Kim, José Silva-Martínez
A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy. IEEE J. Solid State Circuits 48 (6) (2013)
Daniel Gitzel, Rafael Rivera, José Silva-Martínez
Robust compensation scheme for low power capacitor-less low dropout voltage regulator. MWSCAS (2013)
Andreas Larsson, José Silva-Martínez
Efficient calibration scheme for high-resolution pipelined ADCs. MWSCAS (2013)
Kyu-Nam Shim, Jiang Hu, José Silva-Martínez
Dual-Level Adaptive Supply Voltage System for Variation Resilience. IEEE Trans. Very Large Scale Integr. Syst. 21 (6) (2013)
Carlos Zamarreño-Ramos, Raghavendra Kulkarni, José Silva-Martínez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings. IEEE Trans. Biomed. Circuits Syst. 7 (5) (2013)
Saikrishna Ganta, Chang-Joon Park, Daniel Gitzel, Rafael Rivera, José Silva-Martínez
An external capacitor-less low drop-out regulator with superior PSR and fast transient response. MWSCAS (2013)
Richard Turkson, Suraj Prakash, José Silva-Martínez, Herminio Martínez-Garcia
Envelope tracking technique with bang-bang slew-rate enhancer for linear wideband RF PAs. MWSCAS (2013)
Chang-Joon Park, Hemasundar Mohan Geddada, Aydin I. Karsilayan, José Silva-Martínez, Marvin Onabajo
A current-mode flash ADC for low-power continuous-time sigma delta modulators. ISCAS (2013)
Jusung Kim, José Silva-Martínez
Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications. IEEE J. Solid State Circuits 48 (9) (2013)
Kunmo Kim, José Silva-Martínez
-order continuous-time low-pass sigma-delta analog-to-digital converter for wideband applications. MWSCAS (2012)
Ahmed A. Helmy, Hyung-Joon Jeon, Yung-Chung Lo, Andreas J. Larsson, Raghavendra Kulkarni, Jusung Kim, José Silva-Martínez, Kamran Entesari
A Self-Sustained CMOS Microwave Chemical Sensor Using a Frequency Synthesizer. IEEE J. Solid State Circuits 47 (10) (2012)
Haitao Tong, Shanfeng Cheng, Yung-Chung Lo, Aydin I. Karsilayan, José Silva-Martínez
An LC Quadrature VCO Using Capacitive Source Degeneration Coupling to Eliminate Bi-Modal Oscillation. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2012)
José Silva-Martínez, Aydin Ilker Karsilayan, Hemasundar Mohan Geddada
Blocker and jitter tolerant wideband ΣΔ modulators. MWSCAS (2012)
Raghavendra Kulkarni, Jusung Kim, Hyung-Joon Jeon, Jianhong Xiao, José Silva-Martínez
UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations. IEEE Trans. Very Large Scale Integr. Syst. 20 (2) (2012)
Xi Chen, Ehab Ahmed Sobhy, Zhuizhuan Yu, Sebastian Hoyos, José Silva-Martínez, Samuel Palermo, Brian M. Sadler
A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-End. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (3) (2012)
Vijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz
A Continuous Time Multi-Bit Delta Sigma ADC Using Time Domain Quantizer and Feedback Element. IEEE J. Solid State Circuits 46 (3) (2011)
Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, Brian M. Sadler, José Silva-Martínez
Corrections to "A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing". IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2011)
Marvin Onabajo, Josep Altet, Eduardo Aldrete-Vidrio, Diego Mateo, José Silva-Martínez
Electrothermal Design Procedure to Observe RF Circuit Power and Linearity Characteristics With a Homodyne Differential Temperature Sensor. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2011)
Hemasundar Mohan Geddada, José Silva-Martínez, Stewart S. Taylor
Fully balanced low-noise transconductance amplifiers with P1dB > 0dBm in 45nm CMOS. ESSCIRC (2011)
Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, Brian M. Sadler, José Silva-Martínez
A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2011)
Mohamed M. Elsayed, Vijay Dhanasekaran, Manisha Gambhir, José Silva-Martínez, Edgar Sánchez-Sinencio
A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator. IEEE J. Solid State Circuits 46 (9) (2011)
Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Raghavendra Kulkarni, José Silva-Martínez
Voltage mode driver for low power transmission of high speed serial AER Links. ISCAS (2011)
Sebastian Hoyos, Srikanth Pentakota, Zhuizhuan Yu, Ehab Sobhy Abdel Ghany, Xi Chen, Ramy Saad, Samuel Palermo, José Silva-Martínez
Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2011)
Marvin Onabajo, Didac Gómez, Eduardo Aldrete-Vidrio, Josep Altet, Diego Mateo, José Silva-Martínez
Survey of Robustness Enhancement Techniques for Wireless Systems-on-a-Chip and Study of Temperature as Observable for Process Variations. J. Electron. Test. 27 (3) (2011)
Kyu-Nam Shim, Jiang Hu, José Silva-Martínez
A dual-level adaptive supply voltage system for variation resilience. ISQED (2010)
Raghavendra Kulkarni, Jusung Kim, Hyung-Joon Jeon, José Silva-Martínez, Jianhong Xiao
A broadband 470-862 MHz direct conversion CMOS receiver. ISCAS (2010)
Cho-Ying Lu, Marvin Onabajo, Venkata Gadde, Yung-Chung Lo, Hsien-Pu Chen, Vijayaramalingam Periasamy, José Silva-Martínez
A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback. IEEE J. Solid State Circuits 45 (9) (2010)
Mohamed Mobarak, Marvin Onabajo, José Silva-Martínez, Edgar Sánchez-Sinencio
Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications. IEEE J. Solid State Circuits 45 (2) (2010)
Cho-Ying Lu, Jose Fabian Silva-Rivas, Praveena Kode, José Silva-Martínez, Sebastian Hoyos
A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth. IEEE J. Solid State Circuits 45 (6) (2010)
Eduardo Aldrete-Vidrio, Marvin Onabajo, Josep Altet, Diego Mateo, José Silva-Martínez
Non-invasive RF built-in testing using on-chip temperature sensors. ITC (2009)
Rida S. Assaad, José Silva-Martínez
A Graphical Approach to Teaching Amplifier Design at the Undergraduate Level. IEEE Trans. Educ. 52 (1) (2009)
Rida S. Assaad, José Silva-Martínez
Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers. VLSI Design 2009 (2009)
Rida S. Assaad, José Silva-Martínez
The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier. IEEE J. Solid State Circuits 44 (9) (2009)
Yung-Chung Lo, Hsien-Pu Chen, José Silva-Martínez, Sebastian Hoyos
A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider. CICC (2009)
Marvin Onabajo, José Silva-Martínez, Félix O. Fernandez-Rodriguez, Edgar Sánchez-Sinencio
An On-Chip Loopback Block for RF Transceiver Built-In Test. IEEE Trans. Circuits Syst. II Express Briefs (6) (2009)
Vijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz
A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element. ISSCC (2009)
Chinmaya Mishra, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio, José Silva-Martínez
System and Circuit Design for an MB-OFDM UWB Frequency Synthesizer. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2009)
Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio
Design of Three-Stage Class-AB 16ΩHeadphone Driver Capable of Handling Wide Range of Load Capacitance. IEEE J. Solid State Circuits 44 (6) (2009)
Manisha Gambhir, Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio
A low power 1.3GHz dual-path current mode Gm-C filter. CICC (2008)
Alberto Valdes-Garcia, Radhika Venkatasubramanian, José Silva-Martínez, Edgar Sánchez-Sinencio
A Broadband CMOS Amplitude Detector for On-Chip RF Measurements. IEEE Trans. Instrum. Meas. 57 (7) (2008)
Pradeep Kotte Prakasam, Mandar Kulkarni, Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, José Silva-Martínez, Edgar Sánchez-Sinencio
Applications of Multipath Transform-Domain Charge-Sampling Wide-Band Receivers. IEEE Trans. Circuits Syst. II Express Briefs (4) (2008)
Jinghua Li, José Silva-Martínez, Brian Brunn, Shahriar Rokhsaz, Moises E. Robinson
A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2008)
Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio
A 1.2mW 1.6Vpp-Swing Class-AB 16Ω Headphone Driver Capable of Handling Load Capacitance up to 22nF. ISSCC (2008)
David Hernandez-Garduno, José Silva-Martínez
A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer. IEEE J. Solid State Circuits 43 (11) (2008)
Xiaohua Fan, Marvin Onabajo, Félix O. Fernandez-Rodriguez, José Silva-Martínez, Edgar Sánchez-Sinencio
A Current Injection Built-In Test Technique for RF Low-Noise Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2008)
Alberto Valdes-Garcia, Chinmaya Mishra, Faramarz Bahmani, José Silva-Martínez, Edgar Sánchez-Sinencio
An 11-Band 3-10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication. IEEE J. Solid State Circuits 42 (4) (2007)
Shanfeng Cheng, Haitao Tong, José Silva-Martínez, Aydin I. Karsilayan
Steady-State Analysis of Phase-Locked Loops Using Binary Phase Detector. IEEE Trans. Circuits Syst. II Express Briefs (6) (2007)
Shanfeng Cheng, Haitao Tong, José Silva-Martínez, Aydin Ilker Karsilayan
A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz. IEEE J. Solid State Circuits 42 (3) (2007)
Manisha Gambhir, Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio
-C Filters. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2007)
David Hernandez-Garduno, José Silva-Martínez, José L. Ausín
Switched-Capacitor Filters. IEEE Trans. Circuits Syst. II Express Briefs (5) (2007)
Haitao Tong, Shanfeng Cheng, Aydin I. Karsilayan, José Silva-Martínez
An Injection-Locked Frequency Divider With Multiple Highly Nonlinear Injection Stages and Large Division Ratios. IEEE Trans. Circuits Syst. II Express Briefs (4) (2007)
Jianhong Xiao, Guang Zhang, Tianwei Li, José Silva-Martínez
Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting. VLSI Design 2007 (2007)
Artur J. Lewinski, José Silva-Martínez
A 30-MHz Fifth-Order Elliptic Low-Pass CMOS Filter With 65-dB Spurious-Free Dynamic Range. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2007)
David Hernandez-Garduno, José Silva-Martínez
A CMOS 1Gb/s 5-Tap Transversal Equalizer Based on Inductorless 3rd-Order Delay Cells. ISSCC (2007)

José Silva-Martínez.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

José Silva-Martínez