Carlos Briseno-Vidrios

Publication Activity (10 Years)

Years Active: 2015-2019
Publications (10 Years): 9

Top Topics

Broadband Wireless

Quantization Noise

Power Consumption

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Dadian Zhou, Carlos Briseno-Vidrios, Junning Jiang, Chulhyun Park, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. IEEE J. Solid State Circuits 53 (11) (2018)
Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, José Silva-Martínez
A 13bit 200MS/S pipeline ADC with current-mode MDACs. ISCAS (2017)
Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez
A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage. IEEE J. Solid State Circuits 52 (3) (2017)
John S. Mincey, Carlos Briseno-Vidrios, José Silva-Martínez, Christopher T. Rodenbeck
-C Filter Employing Current-Reuse Differential Difference Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs (6) (2017)
Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Negar Rashidi, José Silva-Martínez
High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications. MWSCAS (2017)
Alexander Edward, Qiyuan Liu, Carlos Briseno-Vidrios, Martin Kinyua, Eric G. Soenen, Aydin Ilker Karsilayan, José Silva-Martínez
A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS. IEEE J. Solid State Circuits 52 (2) (2017)
Carlos Briseno-Vidrios, Alexander Edward, Negar Rashidi, José Silva-Martínez
A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer. IEEE J. Solid State Circuits 51 (6) (2016)
Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez
A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique. VLSIC (2015)