Dadian Zhou

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 11

Top Topics

Analog To Digital Converter

Recent Advances

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Instrum. Meas.

Publications

Amr Walid, Dadian Zhou, Jose Silva-Martinez
Matrix-Based Digital Calibration Technique for High-Performance SAR and Pipeline ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (1) (2024)
José Silva-Martínez, Xiaosen Liu, Dadian Zhou
Recent Advances on Linear Low-Dropout Regulators. IEEE Trans. Circuits Syst. II Express Briefs 68 (2) (2021)
Dadian Zhou, Junning Jiang, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator. IEEE J. Solid State Circuits 55 (8) (2020)
Chulhyun Park, Tao Chen, Kyoohyun Noh, Dadian Zhou, Suraj Prakash, Mohammadhossein Naderi Alizadeh, Aydin I. Karsilayan, Degang Chen, Randall L. Geiger, José Silva-Martínez
A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier. IEEE Trans. Circuits Syst. (11) (2020)
Tao Chen, Chulhyun Park, Hao Meng, Dadian Zhou, José Silva-Martínez, Randall L. Geiger, Degang Chen
A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test. IEEE Trans. Instrum. Meas. 69 (6) (2020)
Dadian Zhou, Carlos Briseno-Vidrios, Junning Jiang, Chulhyun Park, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. IEEE J. Solid State Circuits 53 (11) (2018)
Qiyuan Liu, Alexander Edward, Dadian Zhou, José Silva-Martínez
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26 (4) (2018)
Aditya Bommireddipalli, Dadian Zhou, Claudio Talarico, José Silva-Martínez, Aydin I. Karsilayan
A 200MSPS time-interleaved 12-bit ADC system with digital calibration. MWSCAS (2017)
Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, José Silva-Martínez
A 13bit 200MS/S pipeline ADC with current-mode MDACs. ISCAS (2017)
Dadian Zhou, Claudio Talarico, José Silva-Martínez
A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration. SoCC (2016)
Dadian Zhou, Yuhui Shi, Shi Cheng
Brain Storm Optimization Algorithm with Modified Step-Size and Individual Generation. ICSI (1) (2012)